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imxrt-flash/imxrt117x: enable second flash memory & bug fixes
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 - probe second flash memory on port B1
 - set FLEXSPI2 clock to 132 MHz
 - initial flash size fix
 - flexspi_getAddressByPort() fix
 - change FLEXSPI1 SS0 pin on port B1 to SD_B1_4 (SD_B2_05 is already used for DQS on port A1)
 - fix _imxrt_setIOmux() parameters (mode and sion were switched)
 - code style changes

JIRA: NIL-570
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@ziemleszcz
ziemleszcz committed May 13, 2024
1 parent 9f922a2 commit 3b339d4
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Showing 5 changed files with 41 additions and 34 deletions.
2 changes: 1 addition & 1 deletion devices/flash-imxrt/flashdrv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ static inline int minorToPortMask(unsigned int minor)

#if defined(__CPU_IMXRT117X)
case 1:
return flexspi_slBusA1 | flexspi_slBusA2;
return flexspi_slBusB1;
#endif

default:
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8 changes: 4 additions & 4 deletions devices/flash-imxrt/fspi/fspi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -178,8 +178,8 @@ __attribute__((section(".noxip"))) int flexspi_init(flexspi_t *fspi, int instanc
/* Reset flash size, set default 4MB for XIP */
reg = *(fspi->base + flsha1cr0 + i) & (0xff << 23);

if (fspi->slPortMask & (1 << i)) {
reg |= 1 << 16;
if ((fspi->slPortMask & (1 << i)) != 0) {
reg |= (4 * 1024 * 1024) >> 10;
}

*(fspi->base + flsha1cr0 + i) = reg;
Expand Down Expand Up @@ -264,7 +264,7 @@ __attribute__((section(".noxip"))) static addr_t flexspi_getAddressByPort(flexsp
/* FlexSPI use the port (chip select) based on an offset of each memory size */
for (i = 0; i < port; ++i) {
if (fspi->slPortMask & (1 << i)) {
addr += fspi->slFlashSz[i];
addr += (*(fspi->base + flsha1cr0 + i) & ((1 << 23) - 1)) << 10;
}
}

Expand Down Expand Up @@ -423,7 +423,7 @@ __attribute__((section(".noxip"))) ssize_t flexspi_xferExec(flexspi_t *fspi, str
}

/* Clear the instruction pointer */
*(fspi->base + flsha1cr2 + xfer->port) |= 1 << 31;
*(fspi->base + flsha1cr2 + xfer->port) |= 1u << 31;

/* Clear any triggered AHB & IP errors and grant timeouts */
*(fspi->base + intr) |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1);
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61 changes: 34 additions & 27 deletions devices/flash-imxrt/fspi/fspi_rt117x.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,23 +55,25 @@ static void *flexspi_getBase(int instance)

__attribute__((section(".noxip"))) static void flexspi_clockConfig(flexspi_t *fspi)
{
int gate, clk, div, mux, mfd, mfn, state;
int gate, clk, div, mux, mfd, mfn;

switch (fspi->instance) {
case flexspi_instance1:
clk = pctl_clk_flexspi1;
gate = pctl_lpcg_flexspi1;
div = 3; /* SYS_PLL2_CLK / (3 + 1) => 132 MHz */
mux = 5; /* Select main clock: SYS_PLL2_CLK = 528 MHz */
mux = mux_clkroot_flexspi1_syspll2out; /* Select main clock: SYS_PLL2_CLK = 528 MHz */
mfd = 0;
mfn = 0;
break;

case flexspi_instance2:
clk = pctl_clk_flexspi2;
gate = pctl_lpcg_flexspi2;
/* Copy defaults */
_imxrt_getDevClock(clk, &div, &mux, &mfd, &mfn, &state);
div = 3; /* SYS_PLL2_CLK / (3 + 1) => 132 MHz */
mux = mux_clkroot_flexspi2_syspll2out; /* Select main clock: SYS_PLL2_CLK = 528 MHz */
mfd = 0;
mfn = 0;
break;

default:
Expand All @@ -95,26 +97,30 @@ __attribute__((section(".noxip"))) static int flexspi_pinConfig(flexspi_t *fspi)
int pad;
} pin[] = {
/* FlexSPI-1 A1/A2 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1, -1, -1, pctl_mux_gpio_sd_b2_06, 1, pctl_pad_gpio_sd_b2_06 }, /* SS0 */
{ (flexspi_instance1 << 8) | flexspi_slBusA2, -1, -1, pctl_mux_gpio_sd_b2_04, 3, pctl_pad_gpio_sd_b2_04 }, /* SS1 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_dqs_fa, 2, pctl_mux_gpio_sd_b2_05, 1, pctl_pad_gpio_sd_b2_05 }, /* DQS */
{ (flexspi_instance1 << 8) | flexspi_slBusA1, -1, -1, pctl_mux_gpio_sd_b2_06, 1, pctl_pad_gpio_sd_b2_06 }, /* SS0 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_sck_fa, 1, pctl_mux_gpio_sd_b2_07, 1, pctl_pad_gpio_sd_b2_07 }, /* SCLK */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_fa_0, 1, pctl_mux_gpio_sd_b2_08, 1, pctl_pad_gpio_sd_b2_08 }, /* D0 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_fa_1, 1, pctl_mux_gpio_sd_b2_09, 1, pctl_pad_gpio_sd_b2_09 }, /* D1 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_fa_2, 1, pctl_mux_gpio_sd_b2_10, 1, pctl_pad_gpio_sd_b2_10 }, /* D2 */
{ (flexspi_instance1 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi1_fa_3, 1, pctl_mux_gpio_sd_b2_11, 1, pctl_pad_gpio_sd_b2_11 }, /* D3 */

/* FlesSPI-1 B1/B2 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1, -1, -1, pctl_mux_gpio_sd_b1_04, 8, pctl_pad_gpio_sd_b1_04 }, /* SS0 */
{ (flexspi_instance1 << 8) | flexspi_slBusB2, -1, -1, pctl_mux_gpio_sd_b1_03, 9, pctl_pad_gpio_sd_b1_03 }, /* SS1 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_sd_b1_05, 8, pctl_pad_gpio_sd_b1_05 }, /* DQS */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, pctl_isel_flexspi1_sck_fb, 1, pctl_mux_gpio_sd_b2_04, 1, pctl_pad_gpio_sd_b2_04 }, /* SCLK */
{ (flexspi_instance1 << 8) | flexspi_slBusB1, -1, -1, pctl_mux_gpio_sd_b2_05, 3, pctl_pad_gpio_sd_b2_05 }, /* SS0 */
{ (flexspi_instance1 << 8) | flexspi_slBusB2, -1, -1, pctl_mux_gpio_sd_b1_03, 9, pctl_pad_gpio_sd_b1_03 }, /* SS1 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, pctl_isel_flexspi1_fb_0, 1, pctl_mux_gpio_sd_b2_03, 1, pctl_pad_gpio_sd_b2_03 }, /* D0 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, pctl_isel_flexspi1_fb_1, 1, pctl_mux_gpio_sd_b2_02, 1, pctl_pad_gpio_sd_b2_02 }, /* D1 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, pctl_isel_flexspi1_fb_2, 1, pctl_mux_gpio_sd_b2_01, 1, pctl_pad_gpio_sd_b2_01 }, /* D2 */
{ (flexspi_instance1 << 8) | flexspi_slBusB1 | flexspi_slBusB2, pctl_isel_flexspi1_fb_3, 1, pctl_mux_gpio_sd_b2_00, 1, pctl_pad_gpio_sd_b2_00 }, /* D3 */

/* FlexSPI-2 A1/B2 */
/* FlexSPI-2 A1/A2 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1, -1, -1, pctl_mux_gpio_emc_b2_11, 4, pctl_pad_gpio_emc_b2_11 }, /* SS0 */
{ (flexspi_instance2 << 8) | flexspi_slBusA2, -1, -1, pctl_mux_gpio_ad_01, 9, pctl_pad_gpio_ad_01 }, /* SS1 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, -1, -1, pctl_mux_gpio_emc_b2_12, 4, pctl_pad_gpio_emc_b2_12 }, /* DQS */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi2_sck_fa, 0, pctl_mux_gpio_emc_b2_10, 4, pctl_pad_gpio_emc_b2_10 }, /* SCLK */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi2_fa_0, 0, pctl_mux_gpio_emc_b2_13, 4, pctl_pad_gpio_emc_b2_13 }, /* D0 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi2_fa_1, 0, pctl_mux_gpio_emc_b2_14, 4, pctl_pad_gpio_emc_b2_14 }, /* D1 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi2_fa_2, 0, pctl_mux_gpio_emc_b2_15, 4, pctl_pad_gpio_emc_b2_15 }, /* D2 */
Expand All @@ -123,41 +129,42 @@ __attribute__((section(".noxip"))) static int flexspi_pinConfig(flexspi_t *fspi)
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, -1, -1, pctl_mux_gpio_emc_b2_18, 4, pctl_pad_gpio_emc_b2_18 }, /* D5 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, -1, -1, pctl_mux_gpio_emc_b2_19, 4, pctl_pad_gpio_emc_b2_19 }, /* D6 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, -1, -1, pctl_mux_gpio_emc_b2_20, 4, pctl_pad_gpio_emc_b2_20 }, /* D7 */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, -1, -1, pctl_mux_gpio_emc_b2_12, 4, pctl_pad_gpio_emc_b2_12 }, /* DQS */
{ (flexspi_instance2 << 8) | flexspi_slBusA1 | flexspi_slBusA2, pctl_isel_flexspi2_sck_fa, 0, pctl_mux_gpio_emc_b2_10, 4, pctl_pad_gpio_emc_b2_10 }, /* SCLK */
{ (flexspi_instance2 << 8) | flexspi_slBusA1, -1, -1, pctl_mux_gpio_emc_b2_11, 4, pctl_pad_gpio_emc_b2_11 }, /* SS0 */
{ (flexspi_instance2 << 8) | flexspi_slBusA2, -1, -1, pctl_mux_gpio_ad_01, 9, pctl_pad_gpio_ad_01 }, /* SS1 */

/* FlexSPI-2 B1/B2 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_06, 4, pctl_pad_gpio_emc_b2_07 }, /* D0 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_05, 4, pctl_pad_gpio_emc_b2_06 }, /* D1 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_04, 4, pctl_pad_gpio_emc_b2_05 }, /* D2 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_03, 4, pctl_pad_gpio_emc_b2_04 }, /* D3 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_02, 4, pctl_pad_gpio_emc_b2_03 }, /* D4 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1, -1, -1, pctl_mux_gpio_emc_b2_08, 4, pctl_pad_gpio_emc_b2_08 }, /* SS0 */
{ (flexspi_instance2 << 8) | flexspi_slBusB2, -1, -1, pctl_mux_gpio_ad_00, 9, pctl_pad_gpio_ad_00 }, /* SS1 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_07, 4, pctl_pad_gpio_emc_b2_07 }, /* DQS */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_09, 4, pctl_pad_gpio_emc_b2_09 }, /* SCLK */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_06, 4, pctl_pad_gpio_emc_b2_06 }, /* D0 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_05, 4, pctl_pad_gpio_emc_b2_05 }, /* D1 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_04, 4, pctl_pad_gpio_emc_b2_04 }, /* D2 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_03, 4, pctl_pad_gpio_emc_b2_03 }, /* D3 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_02, 4, pctl_pad_gpio_emc_b2_02 }, /* D4 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_01, 4, pctl_pad_gpio_emc_b2_01 }, /* D5 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_00, 4, pctl_pad_gpio_emc_b2_00 }, /* D6 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b1_41, 4, pctl_pad_gpio_emc_b1_41 }, /* D7 */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_sd_b2_07, 8, pctl_pad_gpio_sd_b2_07 }, /* DQS */
{ (flexspi_instance2 << 8) | flexspi_slBusB1 | flexspi_slBusB2, -1, -1, pctl_mux_gpio_emc_b2_09, 4, pctl_pad_gpio_emc_b2_09 }, /* SCLK */
{ (flexspi_instance2 << 8) | flexspi_slBusB1, -1, -1, pctl_mux_gpio_emc_b2_08, 4, pctl_pad_gpio_emc_b2_08 }, /* SS0 */
{ (flexspi_instance2 << 8) | flexspi_slBusB2, -1, -1, pctl_mux_gpio_ad_00, 9, pctl_pad_gpio_ad_00 }, /* SS1 */
};

for (i = 0, done = 0; i < sizeof(pin) / sizeof(pin[0]); ++i) {
if ((pin[i].devMask & ((1 << (fspi->instance - 1)) << 8)) == 0)
if ((pin[i].devMask & ((1 << (fspi->instance - 1)) << 8)) == 0) {
continue;
}

if ((pin[i].devMask & fspi->slPortMask) == 0)
if ((pin[i].devMask & fspi->slPortMask) == 0) {
continue;
}

if (pin[i].isel >= 0)
if (pin[i].isel >= 0) {
_imxrt_setIOisel(pin[i].isel, pin[i].daisy);
}

if (pin[i].mux >= 0)
_imxrt_setIOmux(pin[i].mux, pin[i].mode, 1); /* sion is enabled */
if (pin[i].mux >= 0) {
_imxrt_setIOmux(pin[i].mux, 1, pin[i].mode); /* sion is enabled */
}

if (pin[i].pad >= 0)
if (pin[i].pad >= 0) {
_imxrt_setIOpad(pin[i].pad, 0, 1, 0, 1, 0, 0);
}

done++;
}
Expand Down
2 changes: 1 addition & 1 deletion devices/flash-imxrt/nor/nor.c
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Original file line number Diff line number Diff line change
Expand Up @@ -293,7 +293,7 @@ int nor_probe(flexspi_t *fspi, u8 port, const struct nor_info **pInfo, const cha

res = -ENXIO;

lib_printf("\ndev/flash/nor: Probing flash id 0x%08x", jedecId);
lib_printf("\ndev/flash/nor: Probing flash id 0x%08x on port %d.%d", jedecId, fspi->instance, port);

for (i = 0; i < sizeof(flashInfo) / sizeof(flashInfo[0]); ++i) {
if (flashInfo[i].jedecId == jedecId) {
Expand Down
2 changes: 1 addition & 1 deletion hal/armv7m/imxrt/117x/peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -256,7 +256,7 @@
#define FLASH_FLEXSPI1_INSTANCE 0x1
#define FLASH_FLEXSPI1_QSPI_FREQ 0xc0000007

#define FLASH_FLEXSPI2_MOUNTED 0
#define FLASH_FLEXSPI2_MOUNTED 1
#define FLASH_FLEXSPI2 0x60000000
#define FLASH_SIZE_FLEXSPI2 0x1f800000
#define FLASH_FLEXSPI2_INSTANCE 0x2
Expand Down

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