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dGPU SR-IOV patches #30
dGPU SR-IOV patches #30
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Dependent pr program name is not compatable this pr's program name, for more details please check tracked_on |
Tile-4 is supported by Intel DG2. Support it could benefit performance. Tracked-On: OAM-123143 Signed-off-by: HeYue <yue.he@intel.com>
...which allows setting attach->peer2peer without implementing dynamic importer_ops. Tracked-On: OAM-123143 Signed-off-by: Weifeng Liu <weifeng.liu@intel.com>
TODO: We must always use DMA addresses for the following two reasons: 1. By design we are not allowed to access the struct page backing a scatter list, especially when config DMABUF_DEBUG is turned on in which case the addresses will be mangled by the core. 2. DMA addresses are required for dGPU local memory sharing between host and guest. Tracked-On: OAM-123143 Signed-off-by: Weifeng Liu <weifeng.liu@intel.com>
Dependent pr program name is not compatable this pr's program name, for more details please check tracked_on |
Dependent pr program name is not compatable this pr's program name, for more details please check tracked_on |
Improper Commit Message |
Improper Commit Message |
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LGTM
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Please add "Test Done" part before merge.
This feature is mainly for dGPU local memory sharing between host and guest. Presence of this capability means that the virtio-GPU backend is expecting local memory buffers for scan-out. Tracked-On: OAM-123143 Signed-off-by: Weifeng Liu <weifeng.liu@intel.com>
Done. Please review and approve it! |
Dependent pr program name is not compatable this pr's program name, for more details please check tracked_on |
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Dependent pr program name is not compatable this pr's program name, for more details please check tracked_on |
Add multiple gem obj backs for virtio gpu framebuffer to support multiple planer for some pixel format. Test-done: - GAS; - iGPU VF + virtio-GPU; - iGPU VF + dGPU passthrough. Tracked-On: OAM-124054 Signed-off-by: hangliu1 <hang1.liu@intel.com> Signed-off-by: HeYue <yue.he@intel.com> Signed-off-by: Weifeng Liu <weifeng.liu@intel.com>
Android CI has started Engineering Build for this issue ,Please check the linked Tracked-On issue/Android CI Web for more details. |
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Android CI has started Engineering Build for this issue ,Please check the linked Tracked-On issue/Android CI Web for more details. |
Android CI has started Engineering Build for this issue ,Please check the linked Tracked-On issue/Android CI Web for more details. |
FAILURE: Android CI has completed Engineering Build for this issue.Please check the linked Tracked-On issue/Android CI Web for more details. |
2 similar comments
FAILURE: Android CI has completed Engineering Build for this issue.Please check the linked Tracked-On issue/Android CI Web for more details. |
FAILURE: Android CI has completed Engineering Build for this issue.Please check the linked Tracked-On issue/Android CI Web for more details. |
Android CI has started Engineering Build for this issue ,Please check the linked Tracked-On issue/Android CI Web for more details. |
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LGTM
SUCCESS: Android CI has completed Engineering Build for this issue.Please check the linked Tracked-On issue/Android CI Web for more details. |
Android CI has started MERGE Build for this pr ,Please check the linked Tracked-On issue/Android CI Web for more details. |
5aff8c2
into
projectceladon:celadon/u/mr0/master
Android CI has completed MERGE Build for this pr, build is SUCCESS. Please check the linked Tracked-On issue/Android CI Web for more details. For Binaries: /cactus-absp-or-local/celadon_umr0_master-merge/44 |
This will close #18.