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WIP: Fix path of VCD tcl file when building hardware #269

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WIP: Fix path of VCD tcl file when building hardware #269

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4652dd6
Fix path of VCD tcl file when building hardware
etterli Aug 18, 2025
3362df0
Fix SN_BIN_DIR references
etterli Aug 19, 2025
f0dd6ad
target: Allow to overwrite build dirs
etterli Aug 19, 2025
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4 changes: 2 additions & 2 deletions target/common/gvsoc.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

GVSOC_BUILDDIR ?= work-gvsoc

$(BIN_DIR)/$(TARGET).gvsoc:
$(SN_BIN_DIR)/$(TARGET).gvsoc:
@echo "#!/bin/bash" > $@
@echo 'binary=$$(realpath $$1)' >> $@
@echo 'echo $$binary > .rtlbinary' >> $@
Expand All @@ -18,6 +18,6 @@ $(BIN_DIR)/$(TARGET).gvsoc:

.PHONY: clean-gvsoc
clean-gvsoc:
rm -rf $(BIN_DIR)/$(TARGET).gvsoc $(GVSOC_BUILDDIR)
rm -rf $(SN_BIN_DIR)/$(TARGET).gvsoc $(GVSOC_BUILDDIR)

clean: clean-gvsoc
6 changes: 3 additions & 3 deletions target/common/vcs.mk
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Expand Up @@ -16,7 +16,7 @@ VCS_BENDER_FLAGS += $(COMMON_BENDER_FLAGS) $(COMMON_BENDER_SIM_FLAGS) -t vcs
VCS_SOURCES = $(shell $(BENDER) script flist-plus $(VCS_BENDER_FLAGS) | $(SED_SRCS))

# Directories
VCS_BUILDDIR = $(SN_TARGET_DIR)/work-vcs
VCS_BUILDDIR ?= $(SN_TARGET_DIR)/work-vcs

# Flags
VLOGAN_FLAGS := -assert svaext
Expand All @@ -42,7 +42,7 @@ $(VCS_BUILDDIR):
mkdir -p $@

# Generate RTL prerequisites
$(eval $(call gen_rtl_prerequisites,$(VCS_RTL_PREREQ_FILE),$(VCS_BUILDDIR),$(VCS_BENDER_FLAGS),$(VCS_TOP_MODULE),$(BIN_DIR)/$(TARGET).vcs))
$(eval $(call gen_rtl_prerequisites,$(VCS_RTL_PREREQ_FILE),$(VCS_BUILDDIR),$(VCS_BENDER_FLAGS),$(VCS_TOP_MODULE),$(SN_BIN_DIR)/$(TARGET).vcs))

# Generate compilation script
$(VCS_BUILDDIR)/compile.sh: $(BENDER_YML) $(BENDER_LOCK) | $(VCS_BUILDDIR)
Expand All @@ -62,7 +62,7 @@ vcs: $(SN_BIN_DIR)/$(TARGET).vcs

# Clean all build directories and temporary files for VCS simulation
clean-vcs: clean-work
rm -rf $(BIN_DIR)/$(TARGET).vcs $(VCS_BUILDDIR) vc_hdrs.h
rm -rf $(SN_BIN_DIR)/$(TARGET).vcs $(VCS_BUILDDIR) vc_hdrs.h

clean: clean-vcs

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4 changes: 2 additions & 2 deletions target/common/verilator.mk
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Expand Up @@ -18,7 +18,7 @@ VERILATOR_SEPP ?=
VLT ?= $(VERILATOR_SEPP) verilator

# Directories
VLT_BUILDDIR = $(SN_TARGET_DIR)/work-vlt
VLT_BUILDDIR ?= $(SN_TARGET_DIR)/work-vlt
VLT_FESVR = $(VLT_BUILDDIR)/riscv-isa-sim

# Flags
Expand Down Expand Up @@ -50,7 +50,7 @@ $(VLT_BUILDDIR):
mkdir -p $@

# Generate RTL prerequisites
$(eval $(call gen_rtl_prerequisites,$(VLT_RTL_PREREQ_FILE),$(VLT_BUILDDIR),$(VLT_BENDER_FLAGS),$(VLT_TOP_MODULE),$(BIN_DIR)/$(TARGET).vlt))
$(eval $(call gen_rtl_prerequisites,$(VLT_RTL_PREREQ_FILE),$(VLT_BUILDDIR),$(VLT_BENDER_FLAGS),$(VLT_TOP_MODULE),$(SN_BIN_DIR)/$(TARGET).vlt))

# Build fesvr seperately for verilator since this might use different compilers
# and libraries than modelsim/vcs and
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2 changes: 1 addition & 1 deletion target/common/vsim.mk
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Expand Up @@ -51,7 +51,7 @@ endif

# VCD_DUMP flag enables VCD dump generation
ifeq ($(VCD_DUMP), 1)
VSIM_FLAGS += -do "source $(ROOT)/nonfree/gf12/modelsim/vcd.tcl"
VSIM_FLAGS += -do "source $(SN_ROOT)/nonfree/gf12/modelsim/vcd.tcl"
else
VSIM_FLAGS += -do "run -a"
endif
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4 changes: 2 additions & 2 deletions target/snitch_cluster/experiments/frep/README.md
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Expand Up @@ -16,8 +16,8 @@ make PL_SIM=1 DEBUG=ON vsim

To run the power simulation:
```
BIN_DIR=$PWD/experiments/frep/hw/<cfg>/bin/ make VSIM_BUILDDIR=$PWD/experiments/frep/hw/<cfg>/work-vsim/ clean-vsim
BIN_DIR=$PWD/experiments/frep/hw/<cfg>/bin/ make PL_SIM=1 DEBUG=ON VCD_DUMP=1 VSIM_BUILDDIR=$PWD/experiments/frep/hw/<cfg>/work-vsim/ $BIN_DIR/snitch_cluster.vsim -j
SN_BIN_DIR=$PWD/experiments/frep/hw/<cfg>/bin/ make VSIM_BUILDDIR=$PWD/experiments/frep/hw/<cfg>/work-vsim/ clean-vsim
SN_BIN_DIR=$PWD/experiments/frep/hw/<cfg>/bin/ make PL_SIM=1 DEBUG=ON VCD_DUMP=1 VSIM_BUILDDIR=$PWD/experiments/frep/hw/<cfg>/work-vsim/ $SN_BIN_DIR/snitch_cluster.vsim -j
./experiments.py power.yaml --actions run power -j --run-dir pls_power
```

Expand Down