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fixed nasty bug in valid logic (forgot a [i % n_active_channels])
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@reed-foster
reed-foster committed Oct 11, 2023
1 parent 05cbabb commit 0931312
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Showing 2 changed files with 112 additions and 158 deletions.
255 changes: 103 additions & 152 deletions dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -55,18 +55,19 @@ always @(posedge clk) begin
end
end

task send_samples_full_rate(input int n_samples);
data_in.valid <= '1;
repeat (n_samples) begin
@(posedge clk);
end
data_in.valid <= '0;
endtask

task send_samples_rand_arrivals(input int n_cycles);
repeat (n_cycles) begin
data_in.valid <= $urandom_range(1<<8);
@(posedge clk);
task send_samples(input int n_samples, input bit rand_arrivals);
if (rand_arrivals) begin
repeat (n_samples) begin
data_in.valid <= $urandom_range(1<<8);
@(posedge clk);
end
data_in.valid <= '0;
end else begin
data_in.valid <= '1;
repeat (n_samples) begin
@(posedge clk);
end
data_in.valid <= '0;
end
endtask

Expand Down Expand Up @@ -125,157 +126,107 @@ task check_results(input int banking_mode);
end
endtask

initial begin
reset <= 1'b1;
start <= 1'b0;
stop <= 1'b0;
banking_mode <= '0; // only enable channel 0
data_in.valid <= '0;
repeat (100) @(posedge clk);
reset <= 1'b0;
repeat (50) @(posedge clk);
// start
start <= 1'b1;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(3);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with only channel 0 enabled #");
$display("######################################################");
check_results(0);
// do more tests

// start
start <= 1'b1;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(1024*7+24);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with only channel 0 enabled #");
$display("######################################################");
check_results(0);

// start
start <= 1'b1;
banking_mode <= 3'b1;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(25);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with channels 0 and 1 enabled #");
$display("######################################################");
check_results(1);

// start
start <= 1'b1;
banking_mode <= 3'b1;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(512*7+12);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with channels 0 and 1 enabled #");
$display("######################################################");
check_results(1);

// start
start <= 1'b1;
banking_mode <= 3'b10;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(4);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with channels 0-3 enabled #");
$display("######################################################");
check_results(2);

// start
task start_acq_with_banking_mode(input int mode);
start <= 1'b1;
banking_mode <= 3'b10;
banking_mode <= mode;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(256*7+6);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with channels 0-3 enabled #");
$display("######################################################");
check_results(2);
endtask

// start
start <= 1'b1;
banking_mode <= 3'b11;
config_in.valid <= 1'b1;
@(posedge clk);
initial begin
reset <= 1'b1;
start <= 1'b0;
config_in.valid <= 1'b0;
stop <= 1'b0;
banking_mode <= '0; // only enable channel 0
data_in.valid <= '0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(49);
reset <= 1'b0;
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with all channels enabled #");
$display("######################################################");
check_results(3);

// start
start <= 1'b1;
banking_mode <= 3'b11;
config_in.valid <= 1'b1;
@(posedge clk);
start <= 1'b0;
config_in.valid <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples_full_rate(128*7+3);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with all channels enabled #");
$display("######################################################");
check_results(3);
for (int i = 0; i < 2; i++) begin
start_acq_with_banking_mode(0);
send_samples(37, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with only channel 0 enabled #");
$display("######################################################");
check_results(0);

start_acq_with_banking_mode(0);
send_samples(1024*7+24, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with only channel 0 enabled #");
$display("######################################################");
check_results(0);

start_acq_with_banking_mode(1);
send_samples(25, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with channels 0 and 1 enabled #");
$display("######################################################");
check_results(1);

start_acq_with_banking_mode(1);
send_samples(512*7+12, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with channels 0 and 1 enabled #");
$display("######################################################");
check_results(1);

start_acq_with_banking_mode(2);
send_samples(40, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with channels 0-3 enabled #");
$display("######################################################");
check_results(2);

start_acq_with_banking_mode(2);
send_samples(256*7+6, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with channels 0-3 enabled #");
$display("######################################################");
check_results(2);

start_acq_with_banking_mode(3);
send_samples(49, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with a few samples at #");
$display("# full rate, with all channels enabled #");
$display("######################################################");
check_results(3);

start_acq_with_banking_mode(3);
send_samples(128*7+3, i);
repeat (50) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
$display("# full rate, with all channels enabled #");
$display("######################################################");
check_results(3);
end
$finish;
end

Expand Down
15 changes: 9 additions & 6 deletions dds_test.srcs/sources_1/new/banked_sample_buffer.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,8 @@ module banked_sample_buffer #(
input wire clk, reset,
Axis_Parallel_If.Slave_Simple data_in, // all channels in parallel
Axis_If.Master_Full data_out,
Axis_If.Slave_Simple config_in // {banking_mode, start, stop}
Axis_If.Slave_Simple config_in, // {banking_mode, start, stop}
output logic capture_started
);

// never apply backpressure to discriminator or ADC
Expand All @@ -21,6 +22,7 @@ logic [$clog2(N_BANKING_MODES)-1:0] banking_mode;
logic [$clog2(N_CHANNELS):0] n_active_channels; // extra bit so we can represent N_CHANNELS
assign n_active_channels = 1'b1 << banking_mode;
logic start, stop;
assign capture_started = start;

always_ff @(posedge clk) begin
if (reset) begin
Expand Down Expand Up @@ -48,10 +50,11 @@ always_comb begin
if (stop) begin
banks_stop = 1'b1;
end else begin
// mask so only the final bank filling up can stop capture
// if banking_mode == 0: 1 << N_CHANNELS
// if banking_mode == 1: 3 << (N_CHANNELS - 1)
// if banking_mode == 2: 7 << (N_CHANNELS - 2)
// capture is only stopped when (one of) the final bank(s) fills up
// use the appropriate mask on banks_full to decide when to stop capture
// if banking_mode == 0: mask = 1 << N_CHANNELS
// if banking_mode == 1: mask = 3 << (N_CHANNELS - 1)
// if banking_mode == 2: mask = 7 << (N_CHANNELS - 2)
// ...
full_mask = ((2 << banking_mode) - 1) << (N_CHANNELS - banking_mode);
banks_stop = |(full_mask & banks_full);
Expand Down Expand Up @@ -155,7 +158,7 @@ generate
end
always_ff @(posedge clk) begin
bank_in.data <= data_in.data[i % n_active_channels];
valid_d <= data_in.valid[i];
valid_d <= data_in.valid[i % n_active_channels];
end
end
endgenerate
Expand Down

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