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working on new scalable buffer architecture for flexible multichannel…
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… capture; finished basic unit
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@reed-foster
reed-foster committed Oct 9, 2023
1 parent 32048c9 commit 17b1829
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191 changes: 191 additions & 0 deletions buffer_bank_test_behav.wcfg
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="buffer_bank_test_behav.wdb" id="1">
<top_modules>
<top_module name="buffer_bank_test" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="14,256.833 ns"></ZoomStartTime>
<ZoomEndTime time="14,518.634 ns"></ZoomEndTime>
<Cursor1Time time="14,455.000 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="208"></NameColumnWidth>
<ValueColumnWidth column_width="96"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="40" />
<wvobject type="logic" fp_name="/buffer_bank_test/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/start">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/stop">
<obj_property name="ElementShortName">stop</obj_property>
<obj_property name="ObjectShortName">stop</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/full">
<obj_property name="ElementShortName">full</obj_property>
<obj_property name="ObjectShortName">full</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/sample_count">
<obj_property name="ElementShortName">sample_count[31:0]</obj_property>
<obj_property name="ObjectShortName">sample_count[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/CLK_RATE_HZ">
<obj_property name="ElementShortName">CLK_RATE_HZ[31:0]</obj_property>
<obj_property name="ObjectShortName">CLK_RATE_HZ[31:0]</obj_property>
</wvobject>
<wvobject fp_name="divider298" type="divider">
<obj_property name="label">dut</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/start">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/stop">
<obj_property name="ElementShortName">stop</obj_property>
<obj_property name="ObjectShortName">stop</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/full">
<obj_property name="ElementShortName">full</obj_property>
<obj_property name="ObjectShortName">full</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/state">
<obj_property name="ElementShortName">state[31:0]</obj_property>
<obj_property name="ObjectShortName">state[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/buffer">
<obj_property name="ElementShortName">buffer[0:1023][31:0]</obj_property>
<obj_property name="ObjectShortName">buffer[0:1023][31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/write_addr">
<obj_property name="ElementShortName">write_addr[9:0]</obj_property>
<obj_property name="ObjectShortName">write_addr[9:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/read_addr">
<obj_property name="ElementShortName">read_addr[9:0]</obj_property>
<obj_property name="ObjectShortName">read_addr[9:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/read_stop_addr">
<obj_property name="ElementShortName">read_stop_addr[9:0]</obj_property>
<obj_property name="ObjectShortName">read_stop_addr[9:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/read_addr_d">
<obj_property name="ElementShortName">read_addr_d[2:0][9:0]</obj_property>
<obj_property name="ObjectShortName">read_addr_d[2:0][9:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/data_out_d">
<obj_property name="ElementShortName">data_out_d[3:0][31:0]</obj_property>
<obj_property name="ObjectShortName">data_out_d[3:0][31:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/data_out_valid">
<obj_property name="ElementShortName">data_out_valid[3:0]</obj_property>
<obj_property name="ObjectShortName">data_out_valid[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/buffer_has_data">
<obj_property name="ElementShortName">buffer_has_data</obj_property>
<obj_property name="ObjectShortName">buffer_has_data</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/buffer_bank_test/dut_i/data_out_last">
<obj_property name="ElementShortName">data_out_last</obj_property>
<obj_property name="ObjectShortName">data_out_last</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/BUFFER_DEPTH">
<obj_property name="ElementShortName">BUFFER_DEPTH[31:0]</obj_property>
<obj_property name="ObjectShortName">BUFFER_DEPTH[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/PARALLEL_SAMPLES">
<obj_property name="ElementShortName">PARALLEL_SAMPLES[31:0]</obj_property>
<obj_property name="ObjectShortName">PARALLEL_SAMPLES[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/dut_i/SAMPLE_WIDTH">
<obj_property name="ElementShortName">SAMPLE_WIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">SAMPLE_WIDTH[31:0]</obj_property>
</wvobject>
<wvobject fp_name="divider317" type="divider">
<obj_property name="label">data_in</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/data">
<obj_property name="ElementShortName">data[0:0][15:0]</obj_property>
<obj_property name="ObjectShortName">data[0:0][15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/ready">
<obj_property name="ElementShortName">ready[0:0]</obj_property>
<obj_property name="ObjectShortName">ready[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/valid">
<obj_property name="ElementShortName">valid[0:0]</obj_property>
<obj_property name="ObjectShortName">valid[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/last">
<obj_property name="ElementShortName">last[0:0]</obj_property>
<obj_property name="ObjectShortName">last[0:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/DWIDTH">
<obj_property name="ElementShortName">DWIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">DWIDTH[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_in/PARALLEL_CHANNELS">
<obj_property name="ElementShortName">PARALLEL_CHANNELS[31:0]</obj_property>
<obj_property name="ObjectShortName">PARALLEL_CHANNELS[31:0]</obj_property>
</wvobject>
<wvobject fp_name="divider324" type="divider">
<obj_property name="label">data_out</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/data">
<obj_property name="ElementShortName">data[0:0][15:0]</obj_property>
<obj_property name="ObjectShortName">data[0:0][15:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/ready">
<obj_property name="ElementShortName">ready[0:0]</obj_property>
<obj_property name="ObjectShortName">ready[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/valid">
<obj_property name="ElementShortName">valid[0:0]</obj_property>
<obj_property name="ObjectShortName">valid[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/last">
<obj_property name="ElementShortName">last[0:0]</obj_property>
<obj_property name="ObjectShortName">last[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/DWIDTH">
<obj_property name="ElementShortName">DWIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">DWIDTH[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/buffer_bank_test/data_out/PARALLEL_CHANNELS">
<obj_property name="ElementShortName">PARALLEL_CHANNELS[31:0]</obj_property>
<obj_property name="ObjectShortName">PARALLEL_CHANNELS[31:0]</obj_property>
</wvobject>
</wave_config>
173 changes: 173 additions & 0 deletions dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
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`timescale 1ns / 1ps
module buffer_bank_test ();

logic clk = 0;
localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;

logic reset;

logic start, stop;
logic full;

Axis_If #(.DWIDTH(16), .PARALLEL_CHANNELS(1)) data_in ();
Axis_If #(.DWIDTH(16), .PARALLEL_CHANNELS(1)) data_out ();

buffer_bank #(
.BUFFER_DEPTH(1024),
.PARALLEL_SAMPLES(2),
.SAMPLE_WIDTH(16)
) dut_i (
.clk,
.reset,
.data_in,
.data_out,
.start,
.stop,
.full
);

int sample_count;
logic [15:0] data_sent [$];
logic [15:0] data_received [$];

always @(posedge clk) begin
if (reset) begin
sample_count <= 0;
data_in.data <= '0;
end else begin
// send data
if (data_in.valid && data_in.ready) begin
sample_count <= sample_count + 1;
data_in.data <= $urandom_range(1<<16);
end
// save data that was sent
if (data_in.valid) begin
data_sent.push_front(data_in.data);
end
if (data_out.valid && data_out.ready) begin
data_received.push_front(data_out.data);
end
end
end

task send_samples(input int n_samples, input int delay);
repeat (n_samples) begin
data_in.valid <= 1'b1;
@(posedge clk);
data_in.valid <= 1'b0;
repeat (delay) @(posedge clk);
end
endtask

task do_readout(input bit wait_for_last);
data_out.ready <= 1'b0;
stop <= 1'b1;
@(posedge clk);
stop <= 1'b0;
repeat (500) @(posedge clk);
data_out.ready <= 1'b1;
repeat ($urandom_range(2,4)) @(posedge clk);
data_out.ready <= 1'b0;
repeat ($urandom_range(1,3)) @(posedge clk);
data_out.ready <= 1'b1;
if (wait_for_last) begin
while (!data_out.last) @(posedge clk);
end else begin
repeat (500) @(posedge clk);
end
@(posedge clk);
endtask

task check_results();
$display("data_sent.size() = %0d", data_sent.size());
$display("data_received.size() = %0d", data_received.size());
if ((data_sent.size() + 1) != data_received.size()) begin
$warning("mismatch in amount of sent/received data");
end
if (data_received[$] != data_sent.size()) begin
$warning("incorrect sample count reported by buffer");
end
data_received.pop_back(); // remove sample count
while (data_sent.size() > 0 && data_received.size() > 0) begin
// data from channel 0 can be reordered with data from channel 2
if (data_sent[$] != data_received[$]) begin
$warning("data mismatch error (received %x, sent %x)", data_received[$], data_sent[$]);
end
data_sent.pop_back();
data_received.pop_back();
end
endtask

initial begin
reset <= 1'b1;
start <= 1'b0;
stop <= 1'b0;
data_in.valid <= '0;
repeat (100) @(posedge clk);
reset <= 1'b0;
repeat (50) @(posedge clk);
// start
start <= 1'b1;
@(posedge clk);
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples(128, 3);
repeat (50) @(posedge clk);
do_readout(1'b1);
$display("######################################################");
$display("# checking results for test with a few samples #");
$display("######################################################");
check_results();
// do more tests

// test with one sample
// start
start <= 1'b1;
@(posedge clk);
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples(1, 4);
repeat (50) @(posedge clk);
do_readout(1'b0); // don't wait for last signal
$display("######################################################");
$display("# checking results for test with one sample #");
$display("######################################################");
check_results();

// test with no samples
// start
start <= 1'b1;
@(posedge clk);
start <= 1'b0;
repeat (100) @(posedge clk);
// don't send samples
repeat (50) @(posedge clk);
do_readout(1'b0); // don't wait for last signal
$display("######################################################");
$display("# checking results for test with no samples #");
$display("######################################################");
check_results();

// fill up buffer
// start
start <= 1'b1;
@(posedge clk);
start <= 1'b0;
repeat (100) @(posedge clk);
// send samples
send_samples(1024, 1);
repeat (50) @(posedge clk);
do_readout(1'b1);
$display("######################################################");
$display("# checking results for test with 1024 samples #");
$display("######################################################");
check_results();
repeat (500) @(posedge clk);
$finish;

end

endmodule
11 changes: 6 additions & 5 deletions dds_test.srcs/sources_1/new/axis.sv
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Original file line number Diff line number Diff line change
@@ -1,12 +1,13 @@
// axi-stream interface
interface Axis_If #(
parameter DWIDTH = 32
parameter DWIDTH = 32,
parameter PARALLEL_CHANNELS = 1
);

logic [DWIDTH - 1:0] data;
logic ready;
logic valid;
logic last;
logic [PARALLEL_CHANNELS-1:0][DWIDTH - 1:0] data;
logic [PARALLEL_CHANNELS-1:0] ready;
logic [PARALLEL_CHANNELS-1:0] valid;
logic [PARALLEL_CHANNELS-1:0] last;

modport Master_Full (
input ready,
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