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removed some unused wrapper files
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@reed-foster
reed-foster committed Nov 28, 2023
1 parent e9b9e8d commit 5b2f79f
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Showing 9 changed files with 37 additions and 358 deletions.
65 changes: 0 additions & 65 deletions dds_test.srcs/sources_1/new/banked_sample_buffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -359,68 +359,3 @@ always_ff @(posedge clk) begin
end

endmodule

module banked_sample_buffer_sv #(
parameter int N_CHANNELS = 2,
parameter int BUFFER_DEPTH = 8192,
parameter int PARALLEL_SAMPLES = 16,
parameter int SAMPLE_WIDTH = 16
) (
input wire clk, reset,

input [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] s00_axis_tdata,
input s00_axis_tvalid,
output s00_axis_tready,

input [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] s01_axis_tdata,
input s01_axis_tvalid,
output s01_axis_tready,

output [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] m_axis_tdata,
output m_axis_tvalid,
output m_axis_tlast,
input m_axis_tready,

input [$clog2($clog2(N_CHANNELS)+1)+2-1:0] cfg_axis_tdata,
input cfg_axis_tvalid,
output cfg_axis_tready,

output capture_started
);

Axis_Parallel_If #(.DWIDTH(PARALLEL_SAMPLES*SAMPLE_WIDTH), .PARALLEL_CHANNELS(N_CHANNELS)) data_in ();
Axis_If #(.DWIDTH(PARALLEL_SAMPLES*SAMPLE_WIDTH)) data_out ();
Axis_If #(.DWIDTH($clog2($clog2(N_CHANNELS)+1)+2)) config_in ();

assign data_in.data[0] = s00_axis_tdata;
assign data_in.valid[0] = s00_axis_tvalid;
assign s00_axis_tready = data_in.ready[0];

assign data_in.data[1] = s01_axis_tdata;
assign data_in.valid[1] = s01_axis_tvalid;
assign s01_axis_tready = data_in.ready[1];

assign m_axis_tdata = data_out.data;
assign m_axis_tvalid = data_out.valid;
assign m_axis_tlast = data_out.last;
assign data_out.ready = m_axis_tready;

assign config_in.data = cfg_axis_tdata;
assign config_in.valid = cfg_axis_tvalid;
assign cfg_axis_tready = config_in.ready;

banked_sample_buffer #(
.N_CHANNELS(N_CHANNELS),
.BUFFER_DEPTH(BUFFER_DEPTH),
.PARALLEL_SAMPLES(PARALLEL_SAMPLES),
.SAMPLE_WIDTH(SAMPLE_WIDTH)
) buffer_i (
.clk,
.reset,
.data_in,
.data_out,
.config_in,
.capture_started
);

endmodule
52 changes: 0 additions & 52 deletions dds_test.srcs/sources_1/new/banked_sample_buffer_wrapper.v
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90 changes: 0 additions & 90 deletions dds_test.srcs/sources_1/new/sample_discriminator.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -121,93 +121,3 @@ always_ff @(posedge clk) begin
end

endmodule

module sample_discriminator_sv #(
parameter SAMPLE_WIDTH = 16,
parameter PARALLEL_SAMPLES = 1,
parameter SAMPLE_INDEX_WIDTH = 14,
parameter CLOCK_WIDTH = 50
) (
input wire clk, reset,

input [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] s00_axis_tdata,
input s00_axis_tvalid,
output s00_axis_tready,

input [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] s01_axis_tdata,
input s01_axis_tvalid,
output s01_axis_tready,

output [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] m00_data_axis_tdata,
output m00_data_axis_tvalid,
input m00_data_axis_tready,

output [SAMPLE_WIDTH*PARALLEL_SAMPLES-1:0] m01_data_axis_tdata,
output m01_data_axis_tvalid,
input m01_data_axis_tready,

output [SAMPLE_INDEX_WIDTH+CLOCK_WIDTH-1:0] m00_tstamp_axis_tdata,
output m00_tstamp_axis_tvalid,
input m00_tstamp_axis_tready,

output [SAMPLE_INDEX_WIDTH+CLOCK_WIDTH-1:0] m01_tstamp_axis_tdata,
output m01_tstamp_axis_tvalid,
input m01_tstamp_axis_tready,

input [2*2*SAMPLE_WIDTH-1:0] cfg_axis_tdata,
input cfg_axis_tvalid,
output cfg_axis_tready,

input sample_index_reset
);

Axis_If #(.DWIDTH(N_CHANNELS*SAMPLE_WIDTH*2)) config_in();
Axis_Parallel_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES), .PARALLEL_CHANNELS(N_CHANNELS)) data_in();
Axis_Parallel_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES), .PARALLEL_CHANNELS(N_CHANNELS)) data_out();
Axis_Parallel_If #(.DWIDTH(SAMPLE_INDEX_WIDTH+CLOCK_WIDTH), .PARALLEL_CHANNELS(N_CHANNELS)) timestamps_out();

assign data_in.data[0] = s00_axis_tdata;
assign data_in.valid[0] = s00_axis_tvalid;
assign s00_axis_tready = data_in.ready[0];

assign data_in.data[1] = s01_axis_tdata;
assign data_in.valid[1] = s01_axis_tvalid;
assign s01_axis_tready = data_in.ready[1];

assign m00_data_axis_tdata = data_out.data[0];
assign m00_data_axis_tvalid = data_out.valid[0];
assign data_out.ready[0] = m00_data_axis_tready;

assign m01_data_axis_tdata = data_out.data[1];
assign m01_data_axis_tvalid = data_out.valid[1];
assign data_out.ready[1] = m01_data_axis_tready;

assign m00_tstamp_axis_tdata = timestamps_out.data[0];
assign m00_tstamp_axis_tvalid = timestamps_out.valid[0];
assign timestamps_out.ready[0] = m00_tstamp_axis_tready;

assign m01_tstamp_axis_tdata = timestamps_out.data[1];
assign m01_tstamp_axis_tvalid = timestamps_out.valid[1];
assign timestamps_out.ready[1] = m01_tstamp_axis_tready;

assign config_in.data = cfg_axis_tdata;
assign config_in.valid = cfg_axis_tvalid;
assign cfg_axis_tready = config_in.ready;

sample_discriminator #(
.SAMPLE_WIDTH(SAMPLE_WIDTH),
.PARALLEL_SAMPLES(PARALLEL_SAMPLES),
.N_CHANNELS(N_CHANNELS),
.SAMPLE_INDEX_WIDTH(SAMPLE_INDEX_WIDTH),
.CLOCK_WIDTH(CLOCK_WIDTH),
) disc_i (
.clk,
.reset,
.data_in,
.data_out,
.timestamps_out,
.config_in,
.sample_index_reset
);

endmodule
80 changes: 0 additions & 80 deletions dds_test.srcs/sources_1/new/sample_discriminator_wrapper.v
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47 changes: 37 additions & 10 deletions dds_test.srcs/sources_1/new/timetagging_discriminating_buffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,8 @@ Axis_If #(.DWIDTH($clog2($clog2(N_CHANNELS)+1)+2)) buf_tstamp_cfg ();
Axis_If #(.DWIDTH($clog2($clog2(N_CHANNELS)+1)+2)) buf_data_cfg ();
Axis_If #(.DWIDTH(TIMESTAMP_WIDTH)) buf_tstamp_out ();
Axis_If #(.DWIDTH(SAMPLE_WIDTH*PARALLEL_SAMPLES)) buf_data_out ();
Axis_If #(.DWIDTH(AXI_MM_WIDTH)) buf_tstamp_out_resized ();
Axis_If #(.DWIDTH(AXI_MM_WIDTH)) buf_data_out_resized ();

// share buffer_cfg_in between both buffers so their configuration is synchronized
assign buf_tstamp_cfg.data = buffer_cfg_in.data;
Expand All @@ -37,26 +39,24 @@ assign buf_data_cfg.data = buffer_cfg_in.data;
assign buf_data_cfg.valid = buffer_cfg_in.valid;
assign buffer_cfg_in.ready = 1'b1; // doesn't matter what we do here, since both modules hold ready = 1'b1

// whenever a buffer capture is triggered through the buffer_cfg_in interface,
// reset the sample_index counter in the sample discriminator
logic start;
logic start, start_d;
always_ff @(posedge clk) begin
if (reset) begin
start <= '0;
start_d <= '0;
end else begin
start_d <= start;
if (buffer_cfg_in.ok) begin
start <= buffer_cfg_in.data[1];
end
end
end

// merge both buffer outputs into a word that is AXI_MM_WIDTH bits

sample_discriminator #(
.SAMPLE_WIDTH(SAMPLE_WIDTH),
.PARALLEL_SAMPLES(PARALLEL_SAMPLES),
.N_CHANNELS(N_CHANNELS),
.SAMPLE_INDEX_WIDTH($clog2(DATA_BUFFER_DEPTH*N_CHANNELS)),
.SAMPLE_INDEX_WIDTH(SAMPLE_INDEX_WIDTH),
.CLOCK_WIDTH(TIMESTAMP_WIDTH - SAMPLE_INDEX_WIDTH)
) disc_i (
.clk,
Expand All @@ -65,7 +65,7 @@ sample_discriminator #(
.data_out(disc_data),
.timestamps_out(disc_tstamps),
.config_in(disc_cfg_in),
.sample_index_reset(start)
.sample_index_reset(start & ~start_d) // reset sample_index count whenever a new capture is started
);

banked_sample_buffer #(
Expand All @@ -79,7 +79,7 @@ banked_sample_buffer #(
.data_in(disc_data),
.data_out(buf_data_out),
.config_in(buf_data_cfg),
.stop_aux(buffer_full[0]),
.stop_aux(buffer_full[0]), // stop saving data when timestamp buffer is full
.capture_started(),
.buffer_full(buffer_full[1])
);
Expand All @@ -89,15 +89,42 @@ banked_sample_buffer #(
.BUFFER_DEPTH(TSTAMP_BUFFER_DEPTH),
.PARALLEL_SAMPLES(1),
.N_CHANNELS(N_CHANNELS)
) data_buffer_i (
) timestamp_buffer_i (
.clk,
.reset,
.data_in(disc_tstamps),
.data_out(buf_tstamp_out),
.config_in(buf_tstamp_cfg),
.stop_aux(buffer_full[1]),
.stop_aux(buffer_full[1]), // stop saving timestamps when data buffer is full
.capture_started(),
.buffer_full(buffer_full[0])
);

// merge both buffer outputs into a word that is AXI_MM_WIDTH bits
// first step down/up the width of the outputs

axis_width_converter #(
.DWIDTH_IN(SAMPLE_WIDTH*PARALLEL_SAMPLES),
.UP(),
.DOWN()
) data_width_converter_i (
.clk,
.reset,
.data_in(buf_data_out),
.data_out(buf_tstamp_out_resized)
);

axis_width_converter #(
.DWIDTH_IN(TIMESTAMP_WIDTH),
.UP(),
.DOWN()
) timestamp_width_converter_i (
.clk,
.reset,
.data_in(buf_tstamp_out),
.data_out(buf_tstamp_out_resized)
);

// mux the two outputs

endmodule
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