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update banked sample buffer to output channel id and sample count on …
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…separate cycles for each bank
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@reed-foster
reed-foster committed Oct 13, 2023
1 parent 4deed91 commit cce5391
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Showing 3 changed files with 240 additions and 78 deletions.
91 changes: 55 additions & 36 deletions banked_sample_buffer_test_behav.wcfg
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.385000 us"></ZoomStartTime>
<ZoomEndTime time="788.885001 us"></ZoomEndTime>
<Cursor1Time time="407.885000 us"></Cursor1Time>
<ZoomStartTime time="101.245000 us"></ZoomStartTime>
<ZoomEndTime time="1,682.245001 us"></ZoomEndTime>
<Cursor1Time time="1,418.745000 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="210"></NameColumnWidth>
<ValueColumnWidth column_width="81"></ValueColumnWidth>
<ValueColumnWidth column_width="77"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="20" />
<wvobject type="logic" fp_name="/banked_sample_buffer_test/clk">
Expand Down Expand Up @@ -75,6 +75,16 @@
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/banks_full">
<obj_property name="ElementShortName">banks_full[7:0]</obj_property>
<obj_property name="ObjectShortName">banks_full[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/first">
<obj_property name="ElementShortName">first</obj_property>
<obj_property name="ObjectShortName">first</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/banks_first">
<obj_property name="ElementShortName">banks_first[7:0]</obj_property>
<obj_property name="ObjectShortName">banks_first[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/banks_stop">
<obj_property name="ElementShortName">banks_stop</obj_property>
Expand All @@ -84,70 +94,42 @@
<obj_property name="ElementShortName">bank_select[2:0]</obj_property>
<obj_property name="ObjectShortName">bank_select[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/n_active_channels">
<obj_property name="ElementShortName">n_active_channels[3:0]</obj_property>
<obj_property name="ObjectShortName">n_active_channels[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[0].valid_d ">
<obj_property name="ElementShortName">\bank_i[0].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[0].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[0].full_offset ">
<obj_property name="ElementShortName">\bank_i[0].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[0].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[1].valid_d ">
<obj_property name="ElementShortName">\bank_i[1].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[1].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[1].full_offset ">
<obj_property name="ElementShortName">\bank_i[1].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[1].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[2].valid_d ">
<obj_property name="ElementShortName">\bank_i[2].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[2].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[2].full_offset ">
<obj_property name="ElementShortName">\bank_i[2].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[2].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[3].valid_d ">
<obj_property name="ElementShortName">\bank_i[3].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[3].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[3].full_offset ">
<obj_property name="ElementShortName">\bank_i[3].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[3].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[4].valid_d ">
<obj_property name="ElementShortName">\bank_i[4].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[4].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[4].full_offset ">
<obj_property name="ElementShortName">\bank_i[4].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[4].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[5].valid_d ">
<obj_property name="ElementShortName">\bank_i[5].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[5].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[5].full_offset ">
<obj_property name="ElementShortName">\bank_i[5].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[5].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[6].valid_d ">
<obj_property name="ElementShortName">\bank_i[6].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[6].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[6].full_offset ">
<obj_property name="ElementShortName">\bank_i[6].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[6].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[7].valid_d ">
<obj_property name="ElementShortName">\bank_i[7].valid_d </obj_property>
<obj_property name="ObjectShortName">\bank_i[7].valid_d </obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[7].full_offset ">
<obj_property name="ElementShortName">\bank_i[7].full_offset [2:0]</obj_property>
<obj_property name="ObjectShortName">\bank_i[7].full_offset [2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/N_CHANNELS">
<obj_property name="ElementShortName">N_CHANNELS[31:0]</obj_property>
<obj_property name="ObjectShortName">N_CHANNELS[31:0]</obj_property>
Expand All @@ -168,6 +150,39 @@
<obj_property name="ElementShortName">N_BANKING_MODES[31:0]</obj_property>
<obj_property name="ObjectShortName">N_BANKING_MODES[31:0]</obj_property>
</wvobject>
<wvobject fp_name="divider1380" type="divider">
<obj_property name="label">all_banks_out</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/data">
<obj_property name="ElementShortName">data[7:0][15:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0][15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/ready">
<obj_property name="ElementShortName">ready[7:0]</obj_property>
<obj_property name="ObjectShortName">ready[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/valid">
<obj_property name="ElementShortName">valid[7:0]</obj_property>
<obj_property name="ObjectShortName">valid[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/last">
<obj_property name="ElementShortName">last[7:0]</obj_property>
<obj_property name="ObjectShortName">last[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/ok">
<obj_property name="ElementShortName">ok[7:0]</obj_property>
<obj_property name="ObjectShortName">ok[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/DWIDTH">
<obj_property name="ElementShortName">DWIDTH[31:0]</obj_property>
<obj_property name="ObjectShortName">DWIDTH[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/dut_i/all_banks_out/PARALLEL_CHANNELS">
<obj_property name="ElementShortName">PARALLEL_CHANNELS[31:0]</obj_property>
<obj_property name="ObjectShortName">PARALLEL_CHANNELS[31:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group1455">
<obj_property name="label">data_in</obj_property>
Expand All @@ -185,6 +200,7 @@
<wvobject type="array" fp_name="/banked_sample_buffer_test/data_in/valid">
<obj_property name="ElementShortName">valid[7:0]</obj_property>
<obj_property name="ObjectShortName">valid[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/banked_sample_buffer_test/data_in/last">
<obj_property name="ElementShortName">last[7:0]</obj_property>
Expand Down Expand Up @@ -263,6 +279,7 @@
<wvobject type="group" fp_name="group1452">
<obj_property name="label">bank_0</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[0].bank_i /clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
Expand Down Expand Up @@ -395,6 +412,7 @@
<wvobject type="group" fp_name="group1546">
<obj_property name="label">bank_1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[1].bank_i /clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
Expand Down Expand Up @@ -561,6 +579,7 @@
<wvobject type="group" fp_name="group1628">
<obj_property name="label">bank_2</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/banked_sample_buffer_test/dut_i/\bank_i[2].bank_i /clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
Expand Down
72 changes: 49 additions & 23 deletions dds_test.srcs/sim_1/new/banked_sample_buffer_test.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,22 +5,26 @@ logic clk = 0;
localparam CLK_RATE_HZ = 100_000_000;
always #(0.5s/CLK_RATE_HZ) clk = ~clk;

localparam int N_CHANNELS = 8;
localparam int PARALLEL_SAMPLES = 1;
localparam int SAMPLE_WIDTH = 16;

logic reset;

logic start, stop;
logic [2:0] banking_mode;

assign config_in.data = {banking_mode, start, stop};

Axis_Parallel_If #(.DWIDTH(16), .PARALLEL_CHANNELS(8)) data_in ();
Axis_If #(.DWIDTH(16)) data_out ();
Axis_If #(.DWIDTH(4)) config_in ();
Axis_Parallel_If #(.DWIDTH(PARALLEL_SAMPLES*SAMPLE_WIDTH), .PARALLEL_CHANNELS(N_CHANNELS)) data_in ();
Axis_If #(.DWIDTH(PARALLEL_SAMPLES*SAMPLE_WIDTH)) data_out ();
Axis_If #(.DWIDTH(2+$clog2($clog2(N_CHANNELS)+1))) config_in ();

banked_sample_buffer #(
.N_CHANNELS(8),
.N_CHANNELS(N_CHANNELS),
.BUFFER_DEPTH(1024),
.PARALLEL_SAMPLES(1),
.SAMPLE_WIDTH(16)
.PARALLEL_SAMPLES(PARALLEL_SAMPLES),
.SAMPLE_WIDTH(SAMPLE_WIDTH)
) dut_i (
.clk,
.reset,
Expand All @@ -30,20 +34,22 @@ banked_sample_buffer #(
);


int sample_count [8];
logic [15:0] data_sent [8][$];
logic [15:0] data_received [$];
int sample_count [N_CHANNELS];
logic [PARALLEL_SAMPLES*SAMPLE_WIDTH-1:0] data_sent [N_CHANNELS][$];
logic [PARALLEL_SAMPLES*SAMPLE_WIDTH-1:0] data_received [$];

always @(posedge clk) begin
for (int i = 0; i < 8; i++) begin
for (int i = 0; i < N_CHANNELS; i++) begin
if (reset) begin
sample_count[i] <= 0;
data_in.data[i] <= '0;
end else begin
if (data_in.ok[i]) begin
// send new data
sample_count[i] <= sample_count[i] + 1;
data_in.data[i] <= $urandom_range(1<<16);
for (int j = 0; j < PARALLEL_SAMPLES; j++) begin
data_in.data[i][j*SAMPLE_WIDTH+:SAMPLE_WIDTH] <= $urandom_range({SAMPLE_WIDTH{1'b1}});
end
// save data that was sent
data_sent[i].push_front(data_in.data[i]);
end
Expand All @@ -56,12 +62,29 @@ always @(posedge clk) begin
end

task send_samples(input int n_samples, input bit rand_arrivals);
int samples_sent [N_CHANNELS];
logic [N_CHANNELS-1:0] done;
if (rand_arrivals) begin
repeat (n_samples) begin
data_in.valid <= $urandom_range(1<<8);
// reset
done = '0;
for (int i = 0; i < N_CHANNELS; i++) begin
samples_sent[i] = 0;
end
while (~done) begin
for (int i = 0; i < N_CHANNELS; i++) begin
if (data_in.valid[i]) begin
if (samples_sent[i] == n_samples - 1) begin
done[i] = 1'b1;
end else begin
samples_sent[i] = samples_sent[i] + 1'b1;
end
end
end
data_in.valid <= $urandom_range((1<<N_CHANNELS) - 1) & (~done);
@(posedge clk);
end
data_in.valid <= '0;
@(posedge clk);
end else begin
data_in.valid <= '1;
repeat (n_samples) begin
Expand Down Expand Up @@ -90,19 +113,21 @@ task do_readout(input bit wait_for_last, input int wait_cycles);
repeat (wait_cycles) @(posedge clk);
end
@(posedge clk);
//data_out.ready <= 1'b0;
endtask

task check_results(input int banking_mode);
logic [15:0] temp_sample;
logic [SAMPLE_WIDTH*PARALLEL_SAMPLES:0] temp_sample;
int current_channel, n_samples;
for (int i = 0; i < 8; i++) begin
for (int i = 0; i < N_CHANNELS; i++) begin
$display("data_sent[%0d].size() = %0d", i, data_sent[i].size());
end
$display("data_received.size() = %0d", data_received.size());
while (data_received.size() > 0) begin
temp_sample = data_received.pop_back();
current_channel = temp_sample & 3'h7;
n_samples = temp_sample >> 3;
current_channel = data_received.pop_back();
n_samples = data_received.pop_back();
//current_channel = temp_sample & 3'h7;
//n_samples = temp_sample >> 3;
$display("processing new bank with %0d samples from channel %0d", n_samples, current_channel);
for (int i = 0; i < n_samples; i++) begin
if (data_sent[current_channel][$] != data_received[$]) begin
Expand All @@ -119,7 +144,7 @@ task check_results(input int banking_mode);
$warning("leftover samples in data_sent[%0d]: %0d", i, data_sent[i].size());
end
end
for (int i = (1 << banking_mode); i < 8; i++) begin
for (int i = (1 << banking_mode); i < N_CHANNELS; i++) begin
// flush out any remaining samples in data_sent queue
$display("removing %0d samples from data_sent[%0d]", data_sent[i].size(), i);
while (data_sent[i].size() > 0) data_sent[i].pop_back();
Expand Down Expand Up @@ -159,7 +184,7 @@ initial begin

start_acq_with_banking_mode(0);
send_samples(1024*7+24, i);
repeat (50) @(posedge clk);
repeat (8000) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
Expand All @@ -179,7 +204,7 @@ initial begin

start_acq_with_banking_mode(1);
send_samples(512*7+12, i);
repeat (50) @(posedge clk);
repeat (4000) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
Expand All @@ -199,7 +224,7 @@ initial begin

start_acq_with_banking_mode(2);
send_samples(256*7+6, i);
repeat (50) @(posedge clk);
repeat (2000) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
Expand All @@ -219,7 +244,7 @@ initial begin

start_acq_with_banking_mode(3);
send_samples(128*7+3, i);
repeat (50) @(posedge clk);
repeat (1000) @(posedge clk);
do_readout(1'b1, 500);
$display("######################################################");
$display("# checking results for test with many samples at #");
Expand Down Expand Up @@ -312,6 +337,7 @@ task do_readout(input bit wait_for_last);
repeat (500) @(posedge clk);
end
@(posedge clk);
data_out.ready <= 1'b0;
endtask

task check_results();
Expand Down
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