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add final capacitance tbs
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@rohanku
rohanku committed Sep 12, 2024
1 parent bfd65c7 commit 0acfd68
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Showing 9 changed files with 570 additions and 27 deletions.
2 changes: 2 additions & 0 deletions src/blocks/bitcell_array/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -466,6 +466,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vdd,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand Down Expand Up @@ -501,6 +502,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path),
vmeas_conn: AcImpedanceTbNode::Vss,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand Down
2 changes: 1 addition & 1 deletion src/blocks/decoder/schematic.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ impl Decoder {
let decode = ctx.bus_port("decode", out_bits, Direction::Output);
let decode_b = ctx.bus_port("decode_b", out_bits, Direction::Output);

let port_names = vec!["a", "b", "c"];
let port_names = ["a", "b", "c"];

// Initialize all gates in the decoder tree using BFS.
let mut queue = VecDeque::<(Option<Slice>, &TreeNode)>::new();
Expand Down
160 changes: 151 additions & 9 deletions src/blocks/gate/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -203,9 +203,7 @@ impl Component for TappedGate {
params: &Self::Params,
_ctx: &substrate::data::SubstrateCtx,
) -> substrate::error::Result<Self> {
Ok(TappedGate {
params: params.clone(),
})
Ok(TappedGate { params: *params })
}

fn name(&self) -> arcstr::ArcStr {
Expand Down Expand Up @@ -544,6 +542,27 @@ mod tests {
})
.expect("failed to run pex");

let pu_zin_work_dir = work_dir.join("pu_zin_sim");
let pu_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vss,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pu_zin_work_dir,
)
.expect("failed to write simulation");
let pu_zout_work_dir = work_dir.join("pu_zout_sim");
let pu_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -554,6 +573,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -565,11 +585,33 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-up: Cout = {}, Rout = {}",
"Pull-up: Cin = {}, Cout = {}, Rout = {}",
pu_zin.max_freq_cap(),
pu_zout.max_freq_cap(),
pu_zout.min_freq_res()
);

let pd_zin_work_dir = work_dir.join("pd_zin_sim");
let pd_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vdd,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pd_zin_work_dir,
)
.expect("failed to write simulation");
let pd_zout_work_dir = work_dir.join("pd_zout_sim");
let pd_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -580,6 +622,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -591,7 +634,8 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-down: Cout = {}, Rout = {}",
"Pull-down: Cin = {}, Cout = {}, Rout = {}",
pd_zin.max_freq_cap(),
pd_zout.max_freq_cap(),
pd_zout.min_freq_res()
);
Expand Down Expand Up @@ -794,6 +838,28 @@ mod tests {
})
.expect("failed to run pex");

let pu_zin_work_dir = work_dir.join("pu_zin_sim");
let pu_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vss,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("b"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pu_zin_work_dir,
)
.expect("failed to write simulation");
let pu_zout_work_dir = work_dir.join("pu_zout_sim");
let pu_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -804,6 +870,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -816,11 +883,34 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-up: Cout = {}, Rout = {}",
"Pull-up: Cin = {}, Cout = {}, Rout = {}",
pu_zin.max_freq_cap(),
pu_zout.max_freq_cap(),
pu_zout.min_freq_res()
);

let pd_zin_work_dir = work_dir.join("pd_zin_sim");
let pd_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vdd,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("b"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pd_zin_work_dir,
)
.expect("failed to write simulation");
let pd_zout_work_dir = work_dir.join("pd_zout_sim");
let pd_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -831,6 +921,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -843,7 +934,8 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-down: Cout = {}, Rout = {}",
"Pull-down: Cin = {}, Cout = {}, Rout = {}",
pd_zin.max_freq_cap(),
pd_zout.max_freq_cap(),
pd_zout.min_freq_res()
);
Expand Down Expand Up @@ -907,6 +999,29 @@ mod tests {
})
.expect("failed to run pex");

let pu_zin_work_dir = work_dir.join("pu_zin_sim");
let pu_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vss,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("b"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("c"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pu_zin_work_dir,
)
.expect("failed to write simulation");
let pu_zout_work_dir = work_dir.join("pu_zout_sim");
let pu_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -917,6 +1032,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -930,11 +1046,35 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-up: Cout = {}, Rout = {}",
"Pull-up: Cin = {}, Cout = {}, Rout = {}",
pu_zin.max_freq_cap(),
pu_zout.max_freq_cap(),
pu_zout.min_freq_res()
);

let pd_zin_work_dir = work_dir.join("pd_zin_sim");
let pd_zin = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
&AcImpedanceTbParams {
vdd: 1.8,
fstart: 100.,
fstop: 100e6,
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vdd,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("a"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("b"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("c"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("y"), vec![AcImpedanceTbNode::Floating]),
]),
},
&pd_zin_work_dir,
)
.expect("failed to write simulation");
let pd_zout_work_dir = work_dir.join("pd_zout_sim");
let pd_zout = ctx
.write_simulation::<AcImpedanceTestbench<TappedGate>>(
Expand All @@ -945,6 +1085,7 @@ mod tests {
points: 10,
dut: params,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Floating,
connections: HashMap::from_iter([
(arcstr::literal!("vdd"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("vss"), vec![AcImpedanceTbNode::Vss]),
Expand All @@ -958,7 +1099,8 @@ mod tests {
)
.expect("failed to write simulation");
println!(
"Pull-down: Cout = {}, Rout = {}",
"Pull-down: Cin = {}, Cout = {}, Rout = {}",
pd_zin.max_freq_cap(),
pd_zout.max_freq_cap(),
pd_zout.min_freq_res()
);
Expand Down
30 changes: 18 additions & 12 deletions src/blocks/macros/mod.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -271,7 +271,6 @@ mod tests {
use substrate::component::NoParams;
use substrate::schematic::netlist::NetlistPurpose;

use crate::measure::cap::{self, CapTestbench, TbNode};
use crate::paths::{out_gds, out_spice};
use crate::setup_ctx;
use crate::tests::test_work_dir;
Expand All @@ -282,6 +281,10 @@ mod tests {
#[cfg(feature = "commercial")]
#[ignore = "slow"]
fn test_sense_amp_clk_cap() {
use crate::measure::impedance::{
AcImpedanceTbNode, AcImpedanceTbParams, AcImpedanceTestbench,
};

let ctx = setup_ctx();
let work_dir = test_work_dir("test_sense_amp_clk_cap");

Expand Down Expand Up @@ -317,25 +320,28 @@ mod tests {

let sim_work_dir = work_dir.join("sim");
let cap = ctx
.write_simulation::<CapTestbench<SenseAmp>>(
&cap::TbParams {
idc: 10,
.write_simulation::<AcImpedanceTestbench<SenseAmp>>(
&AcImpedanceTbParams {
fstart: 100.,
fstop: 100e6,
points: 10,
vdd: 1.8,
dut: NoParams,
pex_netlist: Some(pex_netlist_path.clone()),
vmeas_conn: AcImpedanceTbNode::Vss,
connections: HashMap::from_iter([
(arcstr::literal!("VDD"), vec![TbNode::Vdd]),
(arcstr::literal!("VSS"), vec![TbNode::Vss]),
(arcstr::literal!("clk"), vec![TbNode::Vmeas]),
(arcstr::literal!("inn"), vec![TbNode::Vdd]),
(arcstr::literal!("inp"), vec![TbNode::Vss]),
(arcstr::literal!("outp"), vec![TbNode::Floating]),
(arcstr::literal!("outn"), vec![TbNode::Floating]),
(arcstr::literal!("VDD"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("VSS"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("clk"), vec![AcImpedanceTbNode::Vmeas]),
(arcstr::literal!("inn"), vec![AcImpedanceTbNode::Vdd]),
(arcstr::literal!("inp"), vec![AcImpedanceTbNode::Vss]),
(arcstr::literal!("outp"), vec![AcImpedanceTbNode::Floating]),
(arcstr::literal!("outn"), vec![AcImpedanceTbNode::Floating]),
]),
},
&sim_work_dir,
)
.expect("failed to write simulation");
println!("Cclk = {}", cap.cnode);
println!("Cclk = {}", cap.max_freq_cap());
}
}
3 changes: 3 additions & 0 deletions src/blocks/rmux/layout.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,9 @@ impl ReadMux {
tracks.push(rect);
}

ctx.add_port(CellPort::with_shape("bl", pc.v_metal, tracks[1]))?;
ctx.add_port(CellPort::with_shape("br", pc.v_metal, tracks[2]))?;

let mut metadata = Metadata::builder();

for (port, idx) in [("sd_1_1", 1), ("sd_0_0", 2)] {
Expand Down
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