Merge branch 'sram-fixes' of github.com:rahulk29/sram22 into sram-fixes

src/blocks/columns/layout.rs

@@ -359,6 +359,7 @@ impl WmaskPeripherals {
         let ColumnsPhysicalDesign {
             wmask_unit_width,
             nand,
+            ..
         } = &*ctx
             .inner()
             .run_script::<ColumnsPhysicalDesignScript>(&self.params)?;

src/blocks/columns/mod.rs

@@ -136,8 +136,9 @@ impl Component for Column {
 pub struct ColumnsPhysicalDesignScript;
 
 pub struct ColumnsPhysicalDesign {
-    wmask_unit_width: i64,
-    nand: DecoderStageParams,
+    pub cl_max: f64,
+    pub wmask_unit_width: i64,
+    pub nand: DecoderStageParams,
 }
 
 impl Script for ColumnsPhysicalDesignScript {
@@ -172,6 +173,7 @@ impl Script for ColumnsPhysicalDesignScript {
         wmask_buffer_gates.push(wmask_buffer_gates.last().unwrap().clone());
 
         Ok(ColumnsPhysicalDesign {
+            cl_max,
             wmask_unit_width,
             nand: DecoderStageParams {
                 pd: DecoderPhysicalDesignParams {

src/blocks/decoder/mod.rs

@@ -458,6 +458,29 @@ impl PlanTreeNode {
     }
 }
 
+impl DecoderStageParams {
+    pub fn time_constant(&self, cl: f64) -> f64 {
+        let mut delay = 0.0;
+        let mut gates = self.gate.primitive_gates();
+        gates.extend(self.invs.iter().map(|inv| (PrimitiveGateType::Inv, *inv)));
+        for (i, (gt, params)) in gates.iter().enumerate() {
+            let model = primitive_gate_model(*gt);
+            let scale = params.nwidth as f64 / (primitive_gate_params(*gt).nwidth as f64);
+            let cin_next = if i == gates.len() - 1 {
+                cl
+            } else {
+                let (ngt, nparams) = gates[i + 1];
+                let model = primitive_gate_model(ngt);
+                let nscale = nparams.nwidth as f64 / (primitive_gate_params(ngt).nwidth as f64);
+                nscale * model.cin
+            };
+            delay += model.res / scale * (model.cout * scale + cin_next);
+        }
+
+        delay
+    }
+}
+
 impl Component for Decoder {
     type Params = DecoderParams;
     fn new(

src/blocks/sram/mod.rs

@@ -1,4 +1,5 @@
 use self::schematic::fanout_buffer_stage;
+use crate::blocks::columns::ColumnsPhysicalDesignScript;
 use crate::blocks::control::ControlLogicParams;
 use serde::{Deserialize, Serialize};
 use serde_repr::{Deserialize_repr, Serialize_repr};
@@ -280,6 +281,22 @@ impl Script for SramPhysicalDesignScript {
             ..fanout_buffer_stage(horiz_buffer, wrdrven_cap)
         };
 
+        // Add inverters to pc_b buffer to equalize wrdrven and pc_b delay.
+        let col_dsn = ctx.run_script::<ColumnsPhysicalDesignScript>(&col_params)?;
+        let pc_b_delay_invs = ((1.1
+            * (f64::max(
+                col_dsn.nand.time_constant(col_dsn.cl_max)
+                    + write_driver_en_buffer.time_constant(wrdrven_cap),
+                sense_en_buffer.time_constant(saen_cap),
+            ) - pc_b_buffer.time_constant(pc_b_cap))
+            / (INV_MODEL.res * (INV_MODEL.cin + INV_MODEL.cout)))
+            / 2.0)
+            .round() as usize
+            * 2;
+        let mut new_invs = vec![pc_b_buffer.gate.first_gate_sizing(); pc_b_delay_invs];
+        new_invs.extend(pc_b_buffer.invs.drain(..));
+        pc_b_buffer.invs = new_invs;
+
         let col_dec_inst = ctx.instantiate_layout::<Decoder>(&col_decoder)?;
         let pc_b_buffer_inst = ctx.instantiate_layout::<DecoderStage>(&pc_b_buffer)?;
         let sense_en_buffer_inst = ctx.instantiate_layout::<DecoderStage>(&sense_en_buffer)?;