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rearrange control logic pins (#468)
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* rearrange control logic pins

* update deps
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rahulk29 authored Oct 3, 2024
1 parent ce131dc commit 1ddb14e
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Showing 2 changed files with 70 additions and 29 deletions.
26 changes: 13 additions & 13 deletions Cargo.lock

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73 changes: 57 additions & 16 deletions src/blocks/control/layout.rs
Original file line number Diff line number Diff line change
Expand Up @@ -262,9 +262,13 @@ impl ControlLogicReplicaV2 {

// Pins
let num_left_pins = 4;
let num_bot_pins = 6;
let num_bot_pins = 2;
let num_right_pins = 3;
let num_top_pins = 1;
let mut left_pins = Vec::new();
let mut bot_pins = Vec::new();
let mut right_pins = Vec::new();
let mut top_pins = Vec::new();
let top_offset = 2;
let left_offset = 50;

Expand Down Expand Up @@ -307,6 +311,41 @@ impl ControlLogicReplicaV2 {
),
);

// right pins
let vtrack = vtracks.index(
vtracks.track_with_loc(TrackLocator::StartsAfter, group.brect().right() + 3_200),
);
for i in 0..num_right_pins {
let htrack = htracks.index(htrack_start - 2 * (i as i64) - top_offset);
right_pins.push(Rect::from_spans(vtrack, htrack));
ctx.draw_rect(m1, right_pins[i]);
}

router.block(
m2,
Rect::from_spans(
vtrack.expand(true, 2000).expand(false, 140),
group.brect().vspan(),
),
);

// top pins
let htrack = htracks
.index(htracks.track_with_loc(TrackLocator::StartsAfter, group.brect().top()) + 8);
for i in 0..num_top_pins {
let vtrack = vtracks.index(vtrack_start + 2 * (i as i64) + left_offset);
top_pins.push(Rect::from_spans(vtrack, htrack));
ctx.draw_rect(m2, top_pins[i]);
}

router.block(
m1,
Rect::from_spans(
group.brect().hspan(),
htrack.expand(true, 140).expand(false, 2000),
),
);

let clk_pin = left_pins[0];
router.occupy(m1, clk_pin, "clk")?;
let ce_pin = left_pins[1];
Expand All @@ -316,19 +355,21 @@ impl ControlLogicReplicaV2 {
let resetb_pin = left_pins[3];
router.occupy(m1, resetb_pin, "reset_b")?;

let rbl_pin = bot_pins[0];
router.occupy(m2, rbl_pin, "rbl")?;
let rwl_pin = bot_pins[1];
let rwl_pin = top_pins[0];
router.occupy(m2, rwl_pin, "rwl")?;
let pc_b_pin = bot_pins[2];
router.occupy(m2, pc_b_pin, "pc_b")?;
let wlen_pin = bot_pins[3];
router.occupy(m2, wlen_pin, "wlen")?;
let wrdrven_pin = bot_pins[4];

let wrdrven_pin = bot_pins[0];
router.occupy(m2, wrdrven_pin, "wrdrven")?;
let saen_pin = bot_pins[5];
let saen_pin = bot_pins[1];
router.occupy(m2, saen_pin, "saen")?;

let wlen_pin = right_pins[0];
router.occupy(m1, wlen_pin, "wlen")?;
let rbl_pin = right_pins[1];
router.occupy(m1, rbl_pin, "rbl")?;
let pc_b_pin = right_pins[2];
router.occupy(m1, pc_b_pin, "pc_b")?;

// reset_b -> reset_inv.y
let resetb_in = group.port_map().port("reset_inv_a")?.largest_rect(m1)?;
let resetb_in =
Expand Down Expand Up @@ -911,7 +952,7 @@ impl ControlLogicReplicaV2 {

router.route_with_net(ctx, m1, clk_pin, m1, clk_in, "clk")?;
router.route_with_net(ctx, m1, ce_pin, m1, ce_in, "ce")?;
router.route_with_net(ctx, m1, pc_b_out, m2, pc_b_pin, "pc_b")?;
router.route_with_net(ctx, m1, pc_b_out, m1, pc_b_pin, "pc_b")?;
router.route_with_net(ctx, m1, resetb_pin, m1, resetb_in, "reset_b")?;
router.route_with_net(ctx, m1, clkp_b_out, m1, clkp_b_in, "clkp_b")?;
router.route_with_net(ctx, m1, clkp_b_out, m1, clkp_b_in_1, "clkp_b")?;
Expand Down Expand Up @@ -949,10 +990,10 @@ impl ControlLogicReplicaV2 {
router.route_with_net(ctx, m1, clkp_grstb_out, m1, clkp_grstb_in, "clkp_grst_b")?;
router.route_with_net(ctx, m1, wlendb_out, m1, wlendb_in, "wlend_b")?;
router.route_with_net(ctx, m1, wlend_out, m1, wlend_in, "wlend")?;
router.route_with_net(ctx, m1, wlen_out, m2, wlen_pin, "wlen")?;
router.route_with_net(ctx, m1, wlen_out, m1, wlen_pin, "wlen")?;
router.route_with_net(ctx, m1, saen_out, m2, saen_pin, "saen")?;
router.route_with_net(ctx, m2, wrdrven_pin, m1, wrdrven_out, "wrdrven")?;
router.route_with_net(ctx, m2, rbl_pin, m1, rbl_in, "rbl")?;
router.route_with_net(ctx, m1, rbl_pin, m1, rbl_in, "rbl")?;
router.route_with_net(
ctx,
m1,
Expand All @@ -977,11 +1018,11 @@ impl ControlLogicReplicaV2 {
ctx.add_port(CellPort::with_shape("we", m1, we_pin))?;
ctx.add_port(CellPort::with_shape("reset_b", m1, resetb_pin))?;

ctx.add_port(CellPort::with_shape("pc_b", m2, pc_b_pin))?;
ctx.add_port(CellPort::with_shape("rbl", m2, rbl_pin))?;
ctx.add_port(CellPort::with_shape("pc_b", m1, pc_b_pin))?;
ctx.add_port(CellPort::with_shape("rbl", m1, rbl_pin))?;
ctx.add_port(CellPort::with_shape("wrdrven", m2, wrdrven_pin))?;
ctx.add_port(CellPort::with_shape("saen", m2, saen_pin))?;
ctx.add_port(CellPort::with_shape("wlen", m2, wlen_pin))?;
ctx.add_port(CellPort::with_shape("wlen", m1, wlen_pin))?;
ctx.add_port(CellPort::with_shape("rwl", m2, rwl_pin))?;

Ok(())
Expand Down

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