fix formatting

rahulk29 · Sep 20, 2024 · a485b50 · a485b50
1 parent c4ce1f0
commit a485b50
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Showing 4 changed files with 21 additions and 32 deletions.
diff --git a/src/blocks/gate/mod.rs b/src/blocks/gate/mod.rs
@@ -1,19 +1,14 @@
 use std::collections::HashSet;
 
 use serde::{Deserialize, Serialize};
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy},
-        layers::selector::Selector,
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
-
-use super::decoder::{
-    self,
-    layout::{DecoderGate, DecoderGateParams, DecoderTap},
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy};
+use substrate::layout::layers::selector::Selector;
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
+
+use super::decoder::layout::{DecoderGate, DecoderGateParams, DecoderTap};
+use super::decoder::{self};
 
 pub mod layout;
 pub mod schematic;

diff --git a/src/blocks/rmux/mod.rs b/src/blocks/rmux/mod.rs
@@ -1,11 +1,8 @@
 use serde::Serialize;
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy},
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy};
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
 
 mod layout;
 mod schematic;

diff --git a/src/blocks/sram/testbench/mod.rs b/src/blocks/sram/testbench/mod.rs
@@ -417,11 +417,11 @@ impl Testbench for SramTestbench {
                 .unwrap(),
         );
 
-        let signals = (0..self.params.sram.data_width)
-            .map(|i| format!("dout[{i}]"))
-            .collect();
-        ctx.save(Save::Signals(signals));
-        // ctx.save(Save::All);
+        // let signals = (0..self.params.sram.data_width)
+        //     .map(|i| format!("dout[{i}]"))
+        //     .collect();
+        // ctx.save(Save::Signals(signals));
+        ctx.save(Save::All);
 
         let vdd = SiValue::with_precision(self.params.vdd, SiPrefix::Nano);
 

diff --git a/src/blocks/wmux/mod.rs b/src/blocks/wmux/mod.rs
@@ -1,11 +1,8 @@
 use serde::{Deserialize, Serialize};
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy, PortId},
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy, PortId};
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
 
 mod layout;
 mod schematic;