save verilog model

rahulk29 · Oct 14, 2024 · b1642a3 · b1642a3
1 parent 9624441
commit b1642a3
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/blocks/sram/mod.rs b/src/blocks/sram/mod.rs
@@ -663,9 +663,9 @@ pub(crate) mod tests {
                 ctx.write_layout::<Sram>(&$params, &gds_path)
                     .expect("failed to write layout");
 
-                // let verilog_path = out_verilog(&work_dir, &*$params.name());
-                // save_1rw_verilog(&verilog_path,&*$params.name(), &$params)
-                //     .expect("failed to write behavioral model");
+                let verilog_path = out_verilog(&work_dir, &*$params.name());
+                save_1rw_verilog(&verilog_path,&*$params.name(), &$params)
+                    .expect("failed to write behavioral model");
 
                 #[cfg(feature = "commercial")]
                 {