add inverters to write driver delay chain

src/blocks/control/layout.rs

@@ -115,7 +115,10 @@ impl ControlLogicReplicaV2 {
             ("inv_rbl", &inv),
             ("clkp_delay", &ctx.instantiate::<InvChain>(&3)?),
             ("clkpd_inv", &inv),
-            ("clkpd_delay", &ctx.instantiate::<InvChain>(&11)?),
+            (
+                "clkpd_delay",
+                &ctx.instantiate::<InvChain>(&self.params.write_driver_delay_invs)?,
+            ),
             ("mux_wlen_rst", &mux2),
             ("decoder_replica_delay", &ctx.instantiate::<InvChain>(&6)?),
             ("wl_ctl", &sr_latch),

src/blocks/control/mod.rs

@@ -14,6 +14,7 @@ pub struct ControlLogicReplicaV2 {
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Serialize, Deserialize)]
 pub struct ControlLogicParams {
     pub decoder_delay_invs: usize,
+    pub write_driver_delay_invs: usize,
 }
 
 impl Component for ControlLogicReplicaV2 {
@@ -22,6 +23,11 @@ impl Component for ControlLogicReplicaV2 {
         params: &Self::Params,
         _ctx: &substrate::data::SubstrateCtx,
     ) -> substrate::error::Result<Self> {
+        assert_eq!(
+            params.write_driver_delay_invs % 2,
+            1,
+            "write driver delay chain must have an odd number of inverters"
+        );
         Ok(Self { params: *params })
     }
     fn name(&self) -> arcstr::ArcStr {
@@ -140,6 +146,7 @@ pub mod test {
 
     const CONTROL_LOGIC_PARAMS: ControlLogicParams = ControlLogicParams {
         decoder_delay_invs: 20,
+        write_driver_delay_invs: 11,
     };
 
     #[test]

src/blocks/control/schematic.rs

@@ -126,7 +126,7 @@ impl ControlLogicReplicaV2 {
             ])
             .named("clkpd_inv")
             .add_to(ctx);
-        ctx.instantiate::<InvChain>(&11)?
+        ctx.instantiate::<InvChain>(&self.params.write_driver_delay_invs)?
             .with_connections([
                 ("din", clkpd_b),
                 ("dout", clkpdd),

src/blocks/control/testbench/mod.rs

@@ -197,6 +197,7 @@ impl Component for ControlLogicTestbench {
 
         ctx.instantiate::<ControlLogicReplicaV2>(&ControlLogicParams {
             decoder_delay_invs: 20,
+            write_driver_delay_invs: 11,
         })?
         .with_connections([
             ("vdd", vdd),

src/blocks/decoder/mod.rs

@@ -409,6 +409,16 @@ impl TreeNode {
 
         delay
     }
+
+    pub fn max_depth(&self) -> usize {
+        self.gate.primitive_gates().len()
+            + self
+                .children
+                .iter()
+                .map(|c| c.max_depth())
+                .max()
+                .unwrap_or_default()
+    }
 }
 
 impl PlanTreeNode {

src/blocks/sram/mod.rs

@@ -326,6 +326,15 @@ impl Script for SramPhysicalDesignScript {
             .round() as usize
             * 2
             + 2;
+        let write_driver_delay_invs = (f64::max(
+            2.0,
+            0.25 * row_decoder_tree.root.time_constant(wl_cap)
+                / (INV_MODEL.res * (INV_MODEL.cin + INV_MODEL.cout)),
+        ) / 2.0)
+            .round() as usize
+            * 2
+            + 9;
+        println!("using {write_driver_delay_invs} inverters for write driver delay chain");
 
         let wlen_buffer = DecoderStageParams {
             max_width: Some(addr_gate_inst.brect().height()),
@@ -366,7 +375,10 @@ impl Script for SramPhysicalDesignScript {
                 inner: col_params.pc,
             },
             col_params,
-            control: ControlLogicParams { decoder_delay_invs },
+            control: ControlLogicParams {
+                decoder_delay_invs,
+                write_driver_delay_invs,
+            },
         })
     }
 }