correctly join simulation thread handles for sram simulation

src/blocks/gate/mod.rs

@@ -1,19 +1,14 @@
 use std::collections::HashSet;
 
 use serde::{Deserialize, Serialize};
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy},
-        layers::selector::Selector,
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
-
-use super::decoder::{
-    self,
-    layout::{DecoderGate, DecoderGateParams, DecoderTap},
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy};
+use substrate::layout::layers::selector::Selector;
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
+
+use super::decoder::layout::{DecoderGate, DecoderGateParams, DecoderTap};
+use super::decoder::{self};
 
 pub mod layout;
 pub mod schematic;

src/blocks/rmux/mod.rs

@@ -1,11 +1,8 @@
 use serde::Serialize;
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy},
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy};
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
 
 mod layout;
 mod schematic;

src/blocks/sram/mod.rs

@@ -458,7 +458,7 @@ pub(crate) mod tests {
                             let work_dir = work_dir.clone();
                             handles.push(std::thread::spawn(move || {
                                 let ctx = setup_ctx();
-                                let tb = crate::blocks::sram::testbench::tb_params(params, vdd, short, pex_netlist);
+                                let tb = crate::blocks::sram::testbench::tb_params(params, vdd, short, None);
                                 let work_dir = work_dir.join(format!(
                                     "{}_{:.2}_{}",
                                     corner.name(),
@@ -480,6 +480,9 @@ pub(crate) mod tests {
                             }));
                         }
                     }
+                    for handle in handles {
+                        handle.join().expect("failed to join thread");
+                    }
 
                     // crate::abs::run_abstract(
                     //     &work_dir,

src/blocks/sram/testbench/mod.rs

@@ -417,11 +417,11 @@ impl Testbench for SramTestbench {
                 .unwrap(),
         );
 
-        let signals = (0..self.params.sram.data_width)
-            .map(|i| format!("dout[{i}]"))
-            .collect();
-        ctx.save(Save::Signals(signals));
-        // ctx.save(Save::All);
+        // let signals = (0..self.params.sram.data_width)
+        //     .map(|i| format!("dout[{i}]"))
+        //     .collect();
+        // ctx.save(Save::Signals(signals));
+        ctx.save(Save::All);
 
         let vdd = SiValue::with_precision(self.params.vdd, SiPrefix::Nano);
 

src/blocks/wmux/mod.rs

@@ -1,11 +1,8 @@
 use serde::{Deserialize, Serialize};
-use substrate::{
-    component::Component,
-    layout::{
-        cell::{CellPort, PortConflictStrategy, PortId},
-        placement::{align::AlignMode, array::ArrayTiler},
-    },
-};
+use substrate::component::Component;
+use substrate::layout::cell::{CellPort, PortConflictStrategy, PortId};
+use substrate::layout::placement::align::AlignMode;
+use substrate::layout::placement::array::ArrayTiler;
 
 mod layout;
 mod schematic;