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feat(tapa): update scripts for tapa_opt
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vagrantxiao24 committed Sep 9, 2024
1 parent 13916a6 commit bb7a9db
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Showing 5 changed files with 291 additions and 11 deletions.
42 changes: 32 additions & 10 deletions benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/Makefile
Original file line number Diff line number Diff line change
@@ -1,25 +1,47 @@
# Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved.
# The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.

ROOT_DIR := $(shell git rev-parse --show-toplevel)
GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py
TEMP_DIR := $(CURDIR)/build
RS_TARGET := $(CURDIR)/$(TEMP_DIR)/dse/candidate_0/exported/impl/vitis_run_hw
TAPA_XO := $(CURDIR)/design/generated/knn.xo
PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1
PART := xcu280-fsvh2892-2L-e
RUN_FILE := $(CURDIR)/run.py
ROOT_DIR := $(shell git rev-parse --show-toplevel)
KERNEL_NAME := Knn
PLATFORM := xilinx_u280_gen3x16_xdma_1_202211_1
GRP_UTIL := $(ROOT_DIR)/common/util/get_group.py
AB_CONFIG := $(CURDIR)/design/config/ab_config.json
TEMP_DIR := $(CURDIR)/build/$(notdir $(AB_CONFIG))
RS_TARGET := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
TAPA_XO := $(CURDIR)/design/generated/knn.xo
PART := xcu280-fsvh2892-2L-e
BUILD_LOG := $(TEMP_DIR)/build.json
SUCCESS := "Build Successful"
TIMING_RPT := impl_1_hw_bb_locked_timing_summary_routed.rpt
SLACK_GETTER := $(ROOT_DIR)/common/util/get_slack.py
RSPATH := $(CURDIR)
RSXX := rapidstream
RSPYTHON := rapidstream
DEVICE_CONFIG := $(TEMP_DIR)/device.json
DEVICE_GEN := $(CURDIR)/gen_device.py

all: $(RS_TARGET)
$(RSXX) $(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG) -c clk_kernel_00_unbuffered_net -p 3.333
@echo $(SUCCESS)

$(RS_TARGET):$(TAPA_XO)
rapidstream $(RUN_FILE)
$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
mkdir -p $(TEMP_DIR)
cd $(RSPATH) && $(RSXX)-tapaopt \
--work-dir $(TEMP_DIR) \
--tapa-xo-path $< \
--device-config $(DEVICE_CONFIG) \
--autobridge-config $(AB_CONFIG)

$(DEVICE_CONFIG):$(AB_CONFIG)
mkdir -p $(TEMP_DIR)
cd $(RSPATH) && $(RSPYTHON) $(DEVICE_GEN) -i $(AB_CONFIG)

show_groups:
rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \
-o $(TEMP_DIR)/module_types.csv



clean:
rm -rf $(TEMP_DIR) *.log
rm -rf .Xil .run
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204 changes: 204 additions & 0 deletions benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/ab_config.json.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,204 @@
{
"slots": [
{
"area": {
"lut": 170800,
"ff": 381600,
"bram_18k": 768,
"dsp": 1440,
"uram": 128
},
"x": 0,
"y": 0,
"centroid_x_coor": 0,
"centroid_y_coor": 0,
"pblock_ranges": [
"-add { SLICE_X206Y0:SLICE_X232Y59 SLICE_X176Y60:SLICE_X196Y239 SLICE_X117Y180:SLICE_X145Y239 DSP48E2_X25Y18:DSP48E2_X28Y89 DSP48E2_X16Y66:DSP48E2_X19Y89 DSP48E2_X30Y0:DSP48E2_X31Y17 LAGUNA_X24Y0:LAGUNA_X27Y119 LAGUNA_X16Y0:LAGUNA_X19Y119 RAMB18_X11Y24:RAMB18_X11Y95 RAMB18_X8Y72:RAMB18_X9Y95 RAMB18_X12Y0:RAMB18_X13Y23 RAMB36_X11Y12:RAMB36_X11Y47 RAMB36_X8Y36:RAMB36_X9Y47 RAMB36_X12Y0:RAMB36_X13Y11 URAM288_X4Y16:URAM288_X4Y63 URAM288_X2Y48:URAM288_X2Y63 CLOCKREGION_X5Y3:CLOCKREGION_X5Y3 CLOCKREGION_X0Y3:CLOCKREGION_X3Y3 CLOCKREGION_X0Y1:CLOCKREGION_X5Y2 CLOCKREGION_X0Y0:CLOCKREGION_X6Y0 }",
"-remove { CLOCKREGION_X4Y0:CLOCKREGION_X7Y3 }"
],
"north_wire_capacity": 11520,
"south_wire_capacity": 100000000,
"east_wire_capacity": 40320,
"west_wire_capacity": 100000000,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": [
"HBM[0]",
"HBM[1]",
"HBM[2]",
"HBM[3]",
"HBM[4]",
"HBM[5]",
"HBM[6]",
"HBM[7]",
"HBM[8]",
"HBM[9]",
"HBM[10]",
"HBM[11]",
"HBM[12]",
"HBM[13]",
"HBM[14]",
"HBM[15]"
]
},
{
"area": {
"lut": 216960,
"ff": 433920,
"bram_18k": 768,
"dsp": 1536,
"uram": 128
},
"x": 0,
"y": 1,
"centroid_x_coor": 0,
"centroid_y_coor": 150,
"pblock_ranges": [
"-add { SLICE_X176Y240:SLICE_X196Y479 DSP48E2_X25Y90:DSP48E2_X28Y185 LAGUNA_X24Y120:LAGUNA_X27Y359 RAMB18_X11Y96:RAMB18_X11Y191 RAMB36_X11Y48:RAMB36_X11Y95 URAM288_X4Y64:URAM288_X4Y127 CLOCKREGION_X0Y4:CLOCKREGION_X5Y7 }",
"-remove { CLOCKREGION_X4Y4:CLOCKREGION_X7Y7 }"
],
"north_wire_capacity": 11520,
"south_wire_capacity": 11520,
"east_wire_capacity": 40320,
"west_wire_capacity": 100000000,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": []
},
{
"area": {
"lut": 216960,
"ff": 433920,
"bram_18k": 768,
"dsp": 1536,
"uram": 128
},
"x": 0,
"y": 2,
"centroid_x_coor": 0,
"centroid_y_coor": 300,
"pblock_ranges": [
"-add { SLICE_X117Y660:SLICE_X145Y719 SLICE_X176Y480:SLICE_X196Y659 SLICE_X220Y540:SLICE_X221Y599 DSP48E2_X16Y258:DSP48E2_X19Y281 DSP48E2_X25Y186:DSP48E2_X28Y257 LAGUNA_X16Y480:LAGUNA_X19Y599 LAGUNA_X24Y360:LAGUNA_X27Y479 RAMB18_X8Y264:RAMB18_X9Y287 RAMB18_X11Y192:RAMB18_X11Y263 RAMB36_X8Y132:RAMB36_X9Y143 RAMB36_X11Y96:RAMB36_X11Y131 URAM288_X2Y176:URAM288_X2Y191 URAM288_X4Y128:URAM288_X4Y175 CLOCKREGION_X5Y11:CLOCKREGION_X7Y11 CLOCKREGION_X0Y11:CLOCKREGION_X3Y11 CLOCKREGION_X0Y8:CLOCKREGION_X5Y10 CONFIG_SITE_X0Y2:CONFIG_SITE_X0Y2 }",
"-remove { CLOCKREGION_X4Y8:CLOCKREGION_X7Y11 }"
],
"north_wire_capacity": 100000000,
"south_wire_capacity": 11520,
"east_wire_capacity": 41178,
"west_wire_capacity": 100000000,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": []
},
{
"area": {
"lut": 118000,
"ff": 276000,
"bram_18k": 432,
"dsp": 1224,
"uram": 192
},
"x": 1,
"y": 0,
"centroid_x_coor": 100,
"centroid_y_coor": 0,
"pblock_ranges": [
"-add { SLICE_X206Y0:SLICE_X232Y59 SLICE_X176Y60:SLICE_X196Y239 SLICE_X117Y180:SLICE_X145Y239 DSP48E2_X25Y18:DSP48E2_X28Y89 DSP48E2_X16Y66:DSP48E2_X19Y89 DSP48E2_X30Y0:DSP48E2_X31Y17 LAGUNA_X24Y0:LAGUNA_X27Y119 LAGUNA_X16Y0:LAGUNA_X19Y119 RAMB18_X11Y24:RAMB18_X11Y95 RAMB18_X8Y72:RAMB18_X9Y95 RAMB18_X12Y0:RAMB18_X13Y23 RAMB36_X11Y12:RAMB36_X11Y47 RAMB36_X8Y36:RAMB36_X9Y47 RAMB36_X12Y0:RAMB36_X13Y11 URAM288_X4Y16:URAM288_X4Y63 URAM288_X2Y48:URAM288_X2Y63 CLOCKREGION_X5Y3:CLOCKREGION_X5Y3 CLOCKREGION_X0Y3:CLOCKREGION_X3Y3 CLOCKREGION_X0Y1:CLOCKREGION_X5Y2 CLOCKREGION_X0Y0:CLOCKREGION_X6Y0 }",
"-remove { CLOCKREGION_X0Y0:CLOCKREGION_X3Y3 }"
],
"north_wire_capacity": 7125,
"south_wire_capacity": 100000000,
"east_wire_capacity": 100000000,
"west_wire_capacity": 40320,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": [
"HBM[16]",
"HBM[17]",
"HBM[18]",
"HBM[19]",
"HBM[20]",
"HBM[21]",
"HBM[22]",
"HBM[23]",
"HBM[24]",
"HBM[25]",
"HBM[26]",
"HBM[27]",
"HBM[28]",
"HBM[29]",
"HBM[30]",
"HBM[31]",
"CLK_RST"
]
},
{
"area": {
"lut": 147840,
"ff": 295680,
"bram_18k": 384,
"dsp": 1148,
"uram": 192
},
"x": 1,
"y": 1,
"centroid_x_coor": 100,
"centroid_y_coor": 150,
"pblock_ranges": [
"-add { SLICE_X176Y240:SLICE_X196Y479 DSP48E2_X25Y90:DSP48E2_X28Y185 LAGUNA_X24Y120:LAGUNA_X27Y359 RAMB18_X11Y96:RAMB18_X11Y191 RAMB36_X11Y48:RAMB36_X11Y95 URAM288_X4Y64:URAM288_X4Y127 CLOCKREGION_X0Y4:CLOCKREGION_X5Y7 }",
"-remove { CLOCKREGION_X0Y4:CLOCKREGION_X3Y7 }"
],
"north_wire_capacity": 7125,
"south_wire_capacity": 7335,
"east_wire_capacity": 100000000,
"west_wire_capacity": 40320,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": [
"S_AXI_CONTROL"
]
},
{
"area": {
"lut": 165120,
"ff": 330240,
"bram_18k": 432,
"dsp": 1320,
"uram": 192
},
"x": 1,
"y": 2,
"centroid_x_coor": 100,
"centroid_y_coor": 300,
"pblock_ranges": [
"-add { SLICE_X117Y660:SLICE_X145Y719 SLICE_X176Y480:SLICE_X196Y659 SLICE_X220Y540:SLICE_X221Y599 DSP48E2_X16Y258:DSP48E2_X19Y281 DSP48E2_X25Y186:DSP48E2_X28Y257 LAGUNA_X16Y480:LAGUNA_X19Y599 LAGUNA_X24Y360:LAGUNA_X27Y479 RAMB18_X8Y264:RAMB18_X9Y287 RAMB18_X11Y192:RAMB18_X11Y263 RAMB36_X8Y132:RAMB36_X9Y143 RAMB36_X11Y96:RAMB36_X11Y131 URAM288_X2Y176:URAM288_X2Y191 URAM288_X4Y128:URAM288_X4Y175 CLOCKREGION_X5Y11:CLOCKREGION_X7Y11 CLOCKREGION_X0Y11:CLOCKREGION_X3Y11 CLOCKREGION_X0Y8:CLOCKREGION_X5Y10 CONFIG_SITE_X0Y2:CONFIG_SITE_X0Y2 }",
"-remove { CLOCKREGION_X0Y8:CLOCKREGION_X3Y11 }"
],
"north_wire_capacity": 100000000,
"south_wire_capacity": 7335,
"east_wire_capacity": 100000000,
"west_wire_capacity": 41178,
"north_anchor_region": [],
"south_anchor_region": [],
"east_anchor_region": [],
"west_anchor_region": [],
"tags": []
}
],
"rows": 3,
"cols": 2,
"pp_dist": 100,
"part_num": "xcu55c-fsvh2892-2L-e",
"board_name": null,
"platform_name": "xilinx_u55c_gen3x16_xdma_3_202210_1",
"user_pblock_name": "pblock_dynamic_region"
}
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
{
"dse_range_min": 0.7,
"dse_range_max": 0.8,
"partition_strategy": "flat",
"port_pre_assignments": {
".*in_.*" : "HBM[0]",
".*final_out.*" : "HBM[0]",
"s_axi_control_.*": "S_AXI_CONTROL",
"ap_clk": "CLK_RST",
"ap_rst_n": "CLK_RST",
"interrupt": "CLK_RST"
}
}
41 changes: 41 additions & 0 deletions benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/gen_device.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
"""Generate U55c device."""

__copyright__ = """
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved.
The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
""" # noqa

from pathlib import Path
from rapidstream import get_u55c_vitis_device_factory
from rapidstream.assets.floorplan.floorplan_config import FloorplanConfig
import argparse
import os

CUR_DIR = Path(__file__).parent

parser = argparse.ArgumentParser()
parser.add_argument(
"-i", "--input_file", help="default: input_dir", type=str, default="."
)

config_file = os.path.basename(parser.parse_args().input_file)

VITIS_PLATFORM = (
"xilinx_u55c_gen3x16_xdma_3_202210_1" # "xilinx_u280_gen3x16_xdma_1_202211_1"
)

factory = get_u55c_vitis_device_factory(VITIS_PLATFORM)

factory.reduce_slot_area(1, 0, lut=50000, ff=60000)
factory.reduce_slot_area(0, 0, lut=50000, ff=60000)
factory.reduce_slot_area(1, 1, dsp=100)

factory.generate_virtual_device(
Path(f"{CUR_DIR}/build/{config_file}/device.json")
)


#ab_config = FloorplanConfig(
# port_pre_assignments={".*": "SLOT_X0Y0:SLOT_X0Y0"},
#)
#ab_config.save_to_file("test.json")
2 changes: 1 addition & 1 deletion benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/run.py
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
print("Reducing DSP of (1, 1) to make it less congested")
factory.reduce_slot_area(1, 1, dsp=100)

rs = RapidStreamTAPA(f"{CURR_DIR}/build")
rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")

rs.set_virtual_device(factory.generate_virtual_device())
rs.add_xo_file(XO_PATH)
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