feat(digit_Reg): update scripts to support tapaopt

.gitignore

@@ -449,3 +449,4 @@ _x.*/
 *.bit
 bazel-*
 MODULE.bazel*
+work.out

benchmarks/tapa_flow/digit_recognizer/Makefile

@@ -2,63 +2,51 @@
 # The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 
 ROOT_DIR         := $(shell git rev-parse --show-toplevel)
-PLATFORM         := xilinx_u280_gen3x16_xdma_1_202211_1
-PART_NUM         := xcu280-fsvh2892-2L-e
-GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
-RS_SCRIPT        := run.py
 KERNEL_NAME      := digit_recognizer
-SRC_DIR          := $(CURDIR)/design
-TARGET           := hw
+RS_SCRIPT        := $(CURDIR)/run_u55c.py
+AB_CONFIG        := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/ab_config.json
+IMPL_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/impl_config.json
+LINK_CONFIG      := $(CURDIR)/design/config/$(notdir $(RS_SCRIPT))/link_config.ini
+PLATFORM         := xilinx_u55c_gen3x16_xdma_3_202210_1
+GRP_UTIL         := $(ROOT_DIR)/common/util/get_group.py
 TEMP_DIR         := $(CURDIR)/build/$(notdir $(RS_SCRIPT))
-KERNEL_XO        := $(TEMP_DIR)/$(KERNEL_NAME).xo
-KERNEL_XCLBIN    := $(TEMP_DIR)/$(KERNEL_NAME).xclbin
-RS_KERNEL_XCLBIN := $(TEMP_DIR)/dse/candidate_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
-INCLUDE          := -I $(XILINX_HLS)/include
-CFLAGS           := $(INCLUDE) $(OPT_LEVEL)
-CXX              := g++
-HOST             := app.exe
-RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/exported/$(KERNEL_NAME).xo
-TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
+RS_TARGET        := $(TEMP_DIR)/dse/solution_0/vitis_run_hw/$(KERNEL_NAME)_$(PLATFORM).xclbin
+TAPA_XO          := $(CURDIR)/design/digit_recognizer.xo
+BUILD_LOG        := $(TEMP_DIR)/build.json
 SUCCESS          := "Build Successful"
+TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
 SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
-BUILD_LOG        := $(TEMP_DIR)/build.json
-RSXX             := python3
+RSPATH           := $(CURDIR)
+RSXX             := rapidstream
+RSPYTHON         := rapidstream
+DEVICE_CONFIG    := $(TEMP_DIR)/device.json
 
-all: $(RS_KERNEL_XCLBIN)
-	$(RSXX)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
-	echo $(SUCCESS)
 
-$(RS_KERNEL_XCLBIN):$(SRC_DIR)/$(KERNEL_NAME).xo
-	mkdir -p $(TEMP_DIR)
-	$(RSXX) $(RS_SCRIPT)
-
-
-sw_emu: $(KERNEL_XCLBIN) $(HOST)
-	XCL_EMULATION_MODE=sw_emu ./app.exe $<
+all: $(RS_TARGET)
+	cd $(RSPATH) && $(RSPYTHON)	$(SLACK_GETTER) -d $(TEMP_DIR) -i $(TIMING_RPT) -o $(BUILD_LOG)  -c clk_kernel_00_unbuffered_net -p 3.333
+	@echo $(SUCCESS)
 
-xo:$(KERNEL_XO)
-
-$(KERNEL_XO): $(SRC_DIR)/$(KERNEL_NAME).cpp
-	tapac -o $@ $< \
-	--part-num $(PART_NUM) \
-	--clock-period 3.33 \
-	--top $(KERNEL_NAME) \
-	--work-dir $(TEMP_DIR)
-
-csim:$(SRC_DIR)/*.cpp
+$(RS_TARGET):$(TAPA_XO) $(DEVICE_CONFIG)
+	mkdir -p $(TEMP_DIR)
+	cd $(RSPATH) && $(RSXX)-tapaopt \
+    --work-dir $(TEMP_DIR) \
+    --tapa-xo-path $< \
+    --device-config $(DEVICE_CONFIG) \
+    --floorplan-config $(AB_CONFIG) \
+	--single-reg \
+    --run-impl \
+    --implementation-config $(IMPL_CONFIG) \
+    --connectivity-ini $(LINK_CONFIG)
+
+$(DEVICE_CONFIG):$(AB_CONFIG)
 	mkdir -p $(TEMP_DIR)
-	$(CXX) $(INCLUDE) -o $(TEMP_DIR)/main.exe -O2 $^ -ltapa -lfrt -lglog -lgflags -lOpenCL
-	$(TEMP_DIR)/main.exe
+	cd $(RSPATH) && $(RSPYTHON) $(RS_SCRIPT)
 
 show_groups:
 	rapidstream $(GRP_UTIL) -i $(TEMP_DIR)/passes/0-imported.json \
 	-o $(TEMP_DIR)/module_types.csv
 
-m=$(shell date)
 
-git:clean
-	git add .
-	git commit -m "$(m)"
 
 clean:
 	rm -rf $(TEMP_DIR) *.log

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c.py/ab_config.json

@@ -0,0 +1,13 @@
+{
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.7,
+    "partition_strategy": "flat",
+    "port_pre_assignments": {
+        ".*mem_in1.*": "HBM[0]",
+        ".*mem_out_.*": "HBM[0]",
+        "ap_clk": "CLK_RST",
+        "ap_rst_n": "CLK_RST",
+        "interrupt": "CLK_RST",
+        "s_axi_control_.*": "S_AXI_CONTROL"
+    }
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c.py/impl_config.json

@@ -0,0 +1,7 @@
+{
+    "max_workers": 2,
+    "port_to_clock_period": {
+        "ap_clk": 3.33
+    },
+    "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1"
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c.py/link_config.ini

@@ -0,0 +1,3 @@
+[connectivity]
+sp=digit_recognizer.mem_in1:HBM[0]
+sp=digit_recognizer.mem_out:HBM[0]

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_right_left.py/ab_config.json

@@ -0,0 +1,13 @@
+{
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.7,
+    "partition_strategy": "flat",
+    "port_pre_assignments": {
+        ".*mem_in1.*": "SLOT_X0Y0:SLOT_X0Y0",
+        ".*mem_out_.*": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_clk": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_rst_n": "SLOT_X0Y0:SLOT_X0Y0",
+        "interrupt": "SLOT_X0Y0:SLOT_X0Y0",
+        "s_axi_control_.*": "SLOT_X0Y0:SLOT_X0Y0"
+    }
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_right_left.py/impl_config.json

@@ -0,0 +1,7 @@
+{
+    "max_workers": 2,
+    "port_to_clock_period": {
+        "ap_clk": 3.33
+    },
+    "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1"
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_right_left.py/link_config.ini

@@ -0,0 +1,3 @@
+[connectivity]
+sp=digit_recognizer.mem_in1:HBM[0]
+sp=digit_recognizer.mem_out:HBM[0]

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_top_bottom.py/ab_config.json

@@ -0,0 +1,13 @@
+{
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.7,
+    "partition_strategy": "flat",
+    "port_pre_assignments": {
+        ".*mem_in1.*": "SLOT_X0Y0:SLOT_X0Y0",
+        ".*mem_out_.*": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_clk": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_rst_n": "SLOT_X0Y0:SLOT_X0Y0",
+        "interrupt": "SLOT_X0Y0:SLOT_X0Y0",
+        "s_axi_control_.*": "SLOT_X0Y0:SLOT_X0Y0"
+    }
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_top_bottom.py/impl_config.json

@@ -0,0 +1,7 @@
+{
+    "max_workers": 2,
+    "port_to_clock_period": {
+        "ap_clk": 3.33
+    },
+    "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1"
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_top_bottom.py/link_config.ini

@@ -0,0 +1,3 @@
+[connectivity]
+sp=digit_recognizer.mem_in1:HBM[0]
+sp=digit_recognizer.mem_out:HBM[0]

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y0.py/ab_config.json

@@ -0,0 +1,13 @@
+{
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.7,
+    "partition_strategy": "flat",
+    "port_pre_assignments": {
+        ".*mem_in1.*": "SLOT_X0Y0:SLOT_X0Y0",
+        ".*mem_out_.*": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_clk": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_rst_n": "SLOT_X0Y0:SLOT_X0Y0",
+        "interrupt": "SLOT_X0Y0:SLOT_X0Y0",
+        "s_axi_control_.*": "SLOT_X0Y0:SLOT_X0Y0"
+    }
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y0.py/impl_config.json

@@ -0,0 +1,7 @@
+{
+    "max_workers": 2,
+    "port_to_clock_period": {
+        "ap_clk": 3.33
+    },
+    "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1"
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y0.py/link_config.ini

@@ -0,0 +1,3 @@
+[connectivity]
+sp=digit_recognizer.mem_in1:HBM[0]
+sp=digit_recognizer.mem_out:HBM[0]

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y2.py/ab_config.json

@@ -0,0 +1,13 @@
+{
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.7,
+    "partition_strategy": "flat",
+    "port_pre_assignments": {
+        ".*mem_in1.*": "SLOT_X0Y0:SLOT_X0Y0",
+        ".*mem_out_.*": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_clk": "SLOT_X0Y0:SLOT_X0Y0",
+        "ap_rst_n": "SLOT_X0Y0:SLOT_X0Y0",
+        "interrupt": "SLOT_X0Y0:SLOT_X0Y0",
+        "s_axi_control_.*": "SLOT_X0Y0:SLOT_X0Y0"
+    }
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y2.py/impl_config.json

@@ -0,0 +1,7 @@
+{
+    "max_workers": 2,
+    "port_to_clock_period": {
+        "ap_clk": 3.33
+    },
+    "vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1"
+}

benchmarks/tapa_flow/digit_recognizer/design/config/run_u55c_x0y0_x1y2.py/link_config.ini

@@ -0,0 +1,3 @@
+[connectivity]
+sp=digit_recognizer.mem_in1:HBM[0]
+sp=digit_recognizer.mem_out:HBM[0]

benchmarks/tapa_flow/digit_recognizer/design/run_tapa.sh

@@ -0,0 +1,9 @@
+WORK_DIR=work.out
+
+tapa compile \
+  --top digit_recognizer \
+  --part-num xcu55c-fsvh2892-2L-e \
+  --clock-period 3.33 \
+  -o ${WORK_DIR}/digit_recognizer.xo \
+  -f digit_recognizer.cpp \
+  2>&1 | tee tapa.log

benchmarks/tapa_flow/digit_recognizer/run_u55c.py

@@ -0,0 +1,22 @@
+__copyright__ = """
+Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
+The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
+"""
+
+from pathlib import Path
+from rapidstream import get_u55c_vitis_device_factory
+
+CURR_DIR = Path(__file__).parent
+CURR_FILE = Path(__file__).name
+
+VITIS_PLATFORM = (
+    "xilinx_u55c_gen3x16_xdma_3_202210_1"  # "xilinx_u280_gen3x16_xdma_1_202211_1"
+)
+
+factory = get_u55c_vitis_device_factory(VITIS_PLATFORM)
+
+factory.reduce_slot_area(1, 0, lut=50000, ff=60000)
+factory.reduce_slot_area(0, 0, lut=50000, ff=60000)
+factory.reduce_slot_area(1, 1, dsp=100)
+
+factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json"))

benchmarks/tapa_flow/digit_recognizer/run_u280_right_left.py → benchmarks/tapa_flow/digit_recognizer/run_u55c_right_left.py

@@ -3,12 +3,13 @@
 The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
 """
 
-from rapidstream import DeviceFactory, RapidStreamTAPA
+from rapidstream import DeviceFactory
 import os
+from pathlib import Path
 
 CURR_DIR = os.path.dirname(os.path.abspath(__file__))
-INI_PATH = f"{CURR_DIR}/design/link_config.ini"
-VITIS_PLATFORM = "xilinx_u280_gen3x16_xdma_1_202211_1"
+CURR_FILE = os.path.basename(__file__)
+VITIS_PLATFORM = "xilinx_u55c_gen3x16_xdma_3_202210_1"
 KERNEL_NAME = "digit_recognizer"
 XO_PATH = f"{CURR_DIR}/design/{KERNEL_NAME}.xo"
 
@@ -32,7 +33,7 @@
 ]
 
 
-factory = DeviceFactory(row=1, col=2, part_num="xcu280-fsvh2892-2L-e", board_name=None)
+factory = DeviceFactory(row=1, col=2, part_num="xcu55c-fsvh2892-2L-e", board_name=None)
 factory.set_user_pblock_name("pblock_dynamic_region")
 factory.set_slot_pblock(
     0, 0, U280_LOWER2SLOTS + ["-remove CLOCKREGION_X4Y0:CLOCKREGION_X7Y7"]
@@ -50,37 +51,4 @@
 # to reflect the actual available DSPs.
 print("Reducing DSP of (1, 1) to make it less congested")
 factory.reduce_slot_area(1, 0, dsp=100)
-
-rs = RapidStreamTAPA(f"{CURR_DIR}/build/{os.path.basename(__file__)}")
-
-rs.set_virtual_device(factory.generate_virtual_device())
-rs.add_xo_file(XO_PATH)
-rs.set_vitis_platform(VITIS_PLATFORM)
-rs.set_vitis_connectivity_config(INI_PATH)
-
-rs.set_top_module_name(KERNEL_NAME)
-rs.add_clock("ap_clk", 3.33)
-
-rs.add_flatten_targets([KERNEL_NAME])
-
-# Bind ports to HBM 16-31
-right_slot = "SLOT_X1Y0:SLOT_X1Y0"
-left_slot = "SLOT_X0Y0:SLOT_X0Y0"
-# The config file binds the following argument to HBM 0 - 15
-# Thus we need to constrain them to the left side of SLR 0
-# sp=workload.input_bv:HBM[0]
-# sp=workload.key_in:HBM[1]
-# sp=workload.out_bits:HBM[2]
-
-rs.assign_port_to_region(".*", left_slot)
-
-# Xustomize the placement strategy:
-rs.set_placement_strategy("EarlyBlockPlacement")
-
-# Allow two parallel Vitis implementation
-rs.run_dse(
-    max_workers=2,
-    max_dse_limit=0.85,
-    min_dse_limit=0.75,
-    partition_strategy="flat",
-)
+factory.generate_virtual_device(Path(f"{CURR_DIR}/build/{CURR_FILE}/device.json"))