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feat(digit_reg): update scripts for tapaopt
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@@ -449,3 +449,4 @@ _x.*/ | |
*.bit | ||
bazel-* | ||
MODULE.bazel* | ||
work.out |
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13 changes: 13 additions & 0 deletions
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benchmarks/tapa_flow/digit_recognizer/design/config/ab_u55c.json
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{ | ||
"dse_range_max": 0.8, | ||
"dse_range_min": 0.7, | ||
"partition_strategy": "flat", | ||
"port_pre_assignments": { | ||
".*mem_in1.*": "HBM[0]", | ||
".*mem_out_.*": "HBM[0]", | ||
"ap_clk": "CLK_RST", | ||
"ap_rst_n": "CLK_RST", | ||
"interrupt": "CLK_RST", | ||
"s_axi_control_.*": "S_AXI_CONTROL" | ||
} | ||
} |
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benchmarks/tapa_flow/digit_recognizer/design/config/impl_u55c.json
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{ | ||
"max_workers": 2, | ||
"port_to_clock_period": { | ||
"ap_clk": 3.33 | ||
}, | ||
"vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" | ||
} |
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benchmarks/tapa_flow/digit_recognizer/design/config/link_u55c.ini
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[connectivity] | ||
sp=digit_recognizer.mem_in1:HBM[0] | ||
sp=digit_recognizer.mem_out:HBM[0] |
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benchmarks/tapa_flow/digit_recognizer/design/digit_recognizer.xo
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WORK_DIR=work.out | ||
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tapa compile \ | ||
--top digit_recognizer \ | ||
--part-num xcu55c-fsvh2892-2L-e \ | ||
--clock-period 3.33 \ | ||
-o ${WORK_DIR}/digit_recognizer.xo \ | ||
-f digit_recognizer.cpp \ | ||
2>&1 | tee tapa.log |
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__copyright__ = """ | ||
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved. | ||
The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement. | ||
""" | ||
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from pathlib import Path | ||
from rapidstream import get_u55c_vitis_device_factory | ||
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CUR_DIR = Path(__file__).parent | ||
CUR_FILE = Path(__file__).name | ||
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VITIS_PLATFORM = ( | ||
"xilinx_u55c_gen3x16_xdma_3_202210_1" # "xilinx_u280_gen3x16_xdma_1_202211_1" | ||
) | ||
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factory = get_u55c_vitis_device_factory(VITIS_PLATFORM) | ||
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factory.reduce_slot_area(1, 0, lut=50000, ff=60000) | ||
factory.reduce_slot_area(0, 0, lut=50000, ff=60000) | ||
factory.reduce_slot_area(1, 1, dsp=100) | ||
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factory.generate_virtual_device(Path(f"{CUR_DIR}/build/{CUR_FILE}/device.json")) |
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7 changes: 7 additions & 0 deletions
7
benchmarks/tapa_flow/knn_chipknn/k2D_float_8PEs/design/config/impl_config.json
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{ | ||
"max_workers": 2, | ||
"port_to_clock_period": { | ||
"ap_clk": 3.33 | ||
}, | ||
"vitis_platform": "xilinx_u55c_gen3x16_xdma_3_202210_1" | ||
} |
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