fix(tapa): update path

benchmarks/tapa_flow/knn_chipknn/k16D_float_27PEs/README.md

@@ -44,7 +44,7 @@ The RapidStream flow for TAPA requires the following key inputs:
 - **Platform**: The Vitis platform (e.g., `xilinx_u280_gen3x16_xdma_1_202211_1`).
 - **Device**: virtual device define by calling rapidstream APIs based on platform (e.g., `get_u280_vitis_device_factory`).
 - **.xo file**: The `.xo` file generated by TAPA
-- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/link_config.ini)).
+- **Connectivity** (.ini): Include the configuration file for `v++` ([link_config.ini](design/config/run.py/link_config.ini)).
 - **top_module_name**: Top module name for the kernel.
 - **Clock**: All the clock and frequencies.
 - **Flatten Module**: Within a design, not all modules need to be optimized. The flatten module name is the target module rapidstream will optimize.
@@ -70,7 +70,7 @@ rs.add_clock("ap_clk", 3.33)
 rs.add_flatten_targets([kernel_name])
 ```
 
-The HBM AXI port connection is described in [design/config/link_config.ini](design/config/link_config.ini).
+The HBM AXI port connection is described in [design/config/link_config.ini](design/config/run.py/link_config.ini).
 
 ```bash
 [connectivity]
@@ -105,7 +105,7 @@ sp=Knn.final_out_dist:HBM[26]
 sp=Knn.final_out_id:HBM[26]
 ```
 
-As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/link_config.ini) file.
+As a result, it is necessary to assign the kernel ports to the appropriate slots. The Python code below demonstrates this process. For comprehensive linking details, please refer to the [design/config/link_config.ini](design/config/run.py/link_config.ini) file.
 
  ```Python
 right_slot = "SLOT_X1Y0:SLOT_X1Y0"