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retpolanne · Jul 2, 2023 · 8036e51 · 8036e51
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diff --git a/_posts/2023-07-01-the-return-of-renesas.markdown b/_posts/2023-07-01-the-return-of-renesas.markdown
@@ -184,7 +184,7 @@ setpci -v -s 06:00.0 f6.w
 ## A simple workaround
 
 I've also found a quite simple workaround: to fiddle with the FW Download Lock register. This will run before
-any kernel modules load (even the ones on your mkinitcpio). Please change the PCI id for your card (mine is 
+any kernel modules load (even the ones on your mkinitcpio) and also before cryptsetup. Please change the PCI id for your card (mine is 
 06:00.0).
 
 It's pretty simple, and can be set up on boot automatically:
@@ -196,14 +196,14 @@ It's pretty simple, and can be set up on boot automatically:
 ```sh
 [Unit]
 Description=Disable Renesas FW Download
-Before=systemd-modules-load.service
+Before=systemd-modules-load.service systemd-cryptsetup@.service
 
 [Service]
 Type=simple
 ExecStart=/usr/bin/setpci -v -s 06:00.00 f4.b=ff
 
 [Install]
-WantedBy=systemd-modules-load.service
+WantedBy=systemd-modules-load.service systemd-cryptsetup@.service
 ```
 
 3. Enable the service

diff --git a/_posts/2023-07-02-serial-experiments-anne.markdown b/_posts/2023-07-02-serial-experiments-anne.markdown
@@ -0,0 +1,48 @@
+---
+layout: post
+title:  "SerialIO Experiments Anne"
+date:   2023-07-02 10:40:00 -0300
+categories: hardware serial
+tags: hardware serial uart
+---
+
+I love Serial IO and UART ports. I mean, they are so basic: send bits at a specific rate, connect tx and 
+rx, read bits at a specific rate and then BAM, you have a TTY, you have logs. 
+
+However, if timing (or voltage) is not precise, things take a turn to the worse. 
+
+I'm currently thinking about a project where I use the COM port of my motherboard to send the serial logs 
+to an FPGA, which receives these logs and renders them on a display. I kind of like doing things headless 
+while I'm on my Mac and I usually prefer to do things via SSH, but I also want to have the feedback of the 
+serial port. 
+
+In order to test things before the FPGA arrives, I wanted to use a 5V USB to TTL to read the logs from my 
+12V COM port. Nothing fried lol.
+
+It worked, but not consistently... and this is so annoying.
+
+## Analyzing stuff with a Logic Analyzer
+
+Checking some signals in the logic analyzer, I saw the inverse measurement is 50khz for some bits. Some others
+are showing 25khz. 
+
+Things were looking wrong... I've increased the capture to 24MS/s and the bits from the 115200 baud rate were 
+showing... but still had framing errors. 
+
+So! I decided to invert the signal and AAAAAAASUS! 
+
+It was inverted all along... how do I invert this signal to my USB to TTL? It was probably working sometimes
+because of USB-C or something. 
+
+Seems like my CP2102 doesn't support inverting the signal, so I'm buying an FTDI.
+
+# TODO PICS
+
+- Weird Logs
+- Good logs
+- COM pinout
+- ASUS
+
+> *_NOTE_* this post is being updated as I figure stuff out. Expect TODOs here and there.
+
+# References