Skip to content

SvdModel2LstmSDSoCV2-no-unroll #1

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
wants to merge 71 commits into
base: main
Choose a base branch
from
Open

SvdModel2LstmSDSoCV2-no-unroll #1

wants to merge 71 commits into from

Conversation

@ribesstefano
Copy link
Owner

@ribesstefano ribesstefano commented Sep 16, 2021

Removing #pragma HLS UNROLL in the top function SvdModel2LstmSDSoCV2.

The new design should consume lesser area, but it appear to not synthesize properly in Vitis 2021.1.

@ribesstefano
Storage class compiles. Testing call to SvdModel2LstmSDSoCV2() accele…
9e2de2d 
…rator.
@ribesstefano
Call to SvdModel2LstmSDSoCV2() accelerator completes w/out hanging (n…
cebc6de 
…o empty FIFOs).
@ribesstefano
Added call to software model. (There might still be a segmentation-fa…
9211e04 
…ult bug)
@ribesstefano
Added call to HLS emulator software. (There might still be a segmenta…
8836595 
…tion-fault bug)
@ribesstefano
Added check on accelerator output and HLS emulator
b30eab4
@ribesstefano
Started working on synthesizing the design.
1779240
@ribesstefano
Added AXIS lib. Synthesis for SvdModel2LstmSDSoCV2 works.
adabfe7
@ribesstefano
Renamed hls_utils namespace to hlsutils
02e2eec
@ribesstefano
Started working on standalone U-Unit (HlsKernelU). Removed relax_ii_f…
d23301c 
…or_timing from synthesis.
@ribesstefano
Added CMake support for Vitis.
ba22e19
@ribesstefano
Added KernelU test and started playing with hls::vector.
9fb1525
@ribesstefano
Written vectorized U-Kernel.
caf86f3
@ribesstefano
Adjusted scaling of testing values. Still testing HlsVectorKernelU co…
0bf93bd 
…rrectness.
@ribesstefano
Fixed bug in HlsVectorKernelU.
0f516f3
@ribesstefano
Co-Simulation of HlsVectorKernelU completes. There's still one M_AXI …
1bed5f7 
…interface.
@ribesstefano
Added hls::vector to AXIS lib. Added stable version of Scaled SVD app…
b8b637d 
…roximation.
@ribesstefano
Fixed PopVector bug in axis_lib
23d2051
@ribesstefano
AxiStreamInterface class now synthesizes in Vitis and supports Vitis …
7cc1879 
…hls::vectors.
@ribesstefano
Fixed bugs regarding hls::vectors in axis_lib
afc293d
@ribesstefano
KernelU: increased width of output stream. Added PYNQ directory for s…
183349f 
…ub-projects.
@ribesstefano
Asserted TKEEP and TSTRB always HIGH in AxisInterface wrapper. FIFOs …
bea5c83 
…in HlsAxisKernelU properly sized for G >= 1.
@ribesstefano
Added generic Matrix-Vector multiplier kernel.
ada8166
@ribesstefano
Started working on KernelU with different sampling rates.
7250d6e
@ribesstefano
Written input dispatcher for KernelU with different refinements
ce3fa0a
@ribesstefano
Added working KernelU with different samplings. Starting optimizing.
9cf4a61
@ribesstefano
Starting simplifying KernelU with different refinements.
3acd5d8
@ribesstefano
Kernel HlsKernelU_ManySampling synthesizes with II=1. Testing still n…
a3ceb6f 
…eeded.
@ribesstefano
HlsKernelU_ManySampling: fixed TLAST bug.
dc982a0
@ribesstefano
KernelU: Fixed results for N == 2. Bug still present for N > 2.
44d6867
@ribesstefano
KernelU: Fixed bug in calculating R_total.
ac51a32
@ribesstefano
Added DenseSvdKernel.
a7019d8
@ribesstefano
Added test for KernelV.
f47ebf5
@ribesstefano
KernelV: correct simulation for single input.
513c095
@ribesstefano
KernelV: fixed bug with processing multiple inputs.
b0a62b9
@ribesstefano
KernelV: fixed bug with processing multiple inputs.
948878f
@ribesstefano
KernelV: re-arrenged loops order.
783aa4c
@ribesstefano
Setup Pynq directory and added PYNQ kernel_u project.
0fce07b
@ribesstefano
Added kernel_v bitstream to PYNQ projects.
3881708
@ribesstefano
PYNQ/kernel_v: Working hardware with small dimensions
1b3abd2
@ribesstefano
KernelV: fixed cosimulation. Starting moving to Vitis 2021.1 (can't a…
4f36469 
…ccess members of vector arguments anymore).
@ribesstefano
Made kernels compatible with Vitis 2021.1. Added overlay files to PYN…
05e855c 
…Q kernel_v.
@ribesstefano
HlsDenseSvd and HlsLstmSvd are synthesizeable in Vitis 2021.1.
52bd28f
@ribesstefano
Tested HlsKernelV in PYNQ.
a0f3db4
@ribesstefano
AxisLib: added method to push a buffer into a single packet. HlsLstmS…
04a9188 
…vd: fixed II in Non-linear part.
@ribesstefano
PYNQ: Added loading and allocating from binary file into buffer (exam…
c2da42e 
…ple in kernel_v).
@ribesstefano
Added Cosimulation-passing HlsDenseSvd design. Added HlsLstmSvd design.
b158bb8
@ribesstefano
Started working on wrapper function for HlsLstmSvd.
b486ae3
@ribesstefano
HlsDenseSvd: fixed bug in generating TLAST signal for output port.
ab2948e
@ribesstefano
HlsDenseSvd: Added PYNQ hardware files.
4dba96e
@ribesstefano
HlsSvdKernel: added PYNQ files.
62aa779
@ribesstefano
HlsDenseSvd: updated PYNQ hardware files.
15f87ae
@ribesstefano
PYNQ: added notebooks on HlsDenseSvd and HlsSvdKernel. HlsDenseSvd wo…
4610a19 
…rks.
@ribesstefano
HlsLstmSvd: added testbench.
347e58f
@ribesstefano
HlsSvdKernel: added testbench.
fce3883
@ribesstefano
Changed pipeline style to free-running/flushing.
215c3ee
@ribesstefano
HlsSvdKernel: updated PYNQ bitstream file.
c1183b8
@ribesstefano
SvdModel2LstmSDSoCV2: started clean-up and made synthesizeable in Vit…
dd79871 
…is 2021.1.
@ribesstefano
SvdModel2LstmSDSoCV2: removed unroll pragmas in top function, gate di…
20175dd 
…spatcher, u-unit, v-unit and non-linear-unit.
@ribesstefano
SvdModel2LstmSDSoCV2: removed all unrolling
41d2ec0
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@ribesstefano