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This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

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RISC-V Capacity and Bandwidth Controller QoS Register Interface

This document is capturing discussions at the CBQRI TG and attempts to document the baseline. This is not official specification and everything in this document may change.

Quality of Service (QoS) is the minimal end-to-end performance that is guaranteed in advance by a service level agreement (SLA) to an application.

System software needs additional tools to control interference to an application and thereby reduce the variability in performance experienced by one application due to other application’s cache capacity usage, memory bandwidth usage, interconnect bandwidth usage, power usage, etc. through a capacity and bandwidth allocation capability.

Effective use of the capacity and bandwidth allocation capability requires hardware to provide a capacity and bandwidth monitoring capability by which the resource requirements of an application needed to meet a certain performance goal can be characterized.

License

This work is licensed under a Creative Commons Attribution 4.0 International License (CC-BY-4.0). See the LICENSE file for details.

Contributors

Contributors to this specification are contained in the contributors file.

For instructions on how to contribute please see the CONTRIBUTING file.

Dependencies

To build the document, you’ll need the following tools installed on your system:

  make
  asciidoctor-pdf, asciidoctor-bibtex, asciidoctor-diagram and asciidoctor-mathematical
  docker

Cloning and Building the Document

This project uses submodules to include the RISC-V documentation toolchain.

  git clone --recurse-submodule https://github.com/riscv-non-isa/riscv-cbqri.git
  cd ./riscv-cbqri
  make VERSION=v1.0.0 REVMARK=Draft

VERSION: Represents the version of the specification being built. By default, this is set to 'v0.0.0'. You can change this to a different value, like 'v1.0.0', 'v1.1.0', etc., based on the current version of your specification.

REVMARK: This represents a revision marker for the project. Its default value is 'Draft'. You may want to change this to something like 'Release', 'Stable' or 'Ratified'.

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This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

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