Add DCSR.MPRVEN support #1882
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Add DCSR.MPRVEN support #1882
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I've also added tests targeting this feature: riscv-software-src/riscv-tests#599 |
Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN while executing ROM To avoid unwanted address translation in while debug_rom.S executed DCSR.MPRVEN bit has to be cleared on entry and restored on exit. Updated version of debug_rom.S does the following: * On _entry: clears DCSR.MPRVEN bit, stores previous DCSR value to S1 and stores previous S1 value to DSCRATCH01 * On _exception: restores S1 value from DSCRATCH01 * On _resume/going: restores S1 and DCSR values Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
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@aswaterman, @rtwfroody, would you kindly take a look? |
aswaterman
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Dec 20, 2024
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I had thought that not using dscratch1 was a goal of this sample debug ROM, but I'll defer to @rtwfroody
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Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status).
This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2).
This change:
Commit's changes:
To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared on entry and restored on exit.
Updated version of debug_rom.S does the following: