Merge pull request #1645 from riscv/fixes-for-sscofpmt-smcntrpmf

Adds back bits 57 & 56
riscv · Sep 24, 2024 · e867a4e · e867a4e
2 parents 1745bbf + 59f59ed
commit e867a4e
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Showing 2 changed files with 6 additions and 4 deletions.
diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc
@@ -19,7 +19,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil
 [cols="^1,^1,^1,^1,^1,^1,^5",stripes=even,options="header"]
 |====
 |63 |62 |61 |60 |59 |58 |57:0
-|0 |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ 
+|0 |MINH |SINH |UINH |VSINH |VUINH |_WPRI_
 |====
 
 [cols="15%,85%",options="header"]

diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc
@@ -30,10 +30,10 @@ interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.
 
 The following bits are added to `mhpmevent`:
 
-[cols="^1,^1,^1,^1,^1,^1",stripes=even,options="header"]
+[cols="^1,^1,^1,^1,^1,^1,^1,^1",stripes=even,options="header"]
 |====
-|63 |62 |61 |60 |59 |58
-|OF |MINH |SINH |UINH |VSINH |VUINH
+|63 |62 |61 |60 |59 |58 |57 |56
+|OF |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ |_WPRI_
 |====
 
 [cols="15%,85%",options="header"]
@@ -45,6 +45,8 @@ The following bits are added to `mhpmevent`:
 | UINH | If set, then counting of events in U-mode is inhibited
 | VSINH | If set, then counting of events in VS-mode is inhibited
 | VUINH | If set, then counting of events in VU-mode is inhibited
+| _WPRI_ | Reserved
+| _WPRI_ | Reserved
 |====
 
 For each ``x``INH bit, if the associated privilege mode is not implemented,