converting bytefield from edn to adoc type files

src/c-st-ext.adoc

@@ -958,15 +958,15 @@ RV128
 
 [[rvc-instr-table0]]
 .Instruction listing for RVC, Quadrant 0
-include::images/bytefield/rvc-instr-quad0.adoc[]
+include::images/bytefield/rvc-instr-quad0.edn[]
 //include::images/bytefield/rvc-instr-quad0.png[]
 
 [[rvc-instr-table1]]
 .Instruction listing for RVC, Quadrant 1
-include::images/bytefield/rvc-instr-quad1.adoc[]
+include::images/bytefield/rvc-instr-quad1.edn[]
 //include::images/bytefield/rvc-instr-quad1.png[]
 
 [[rvc-instr-table2]]
 .Instruction listing for RVC, Quadrant 2
-include::images/bytefield/rvc-instr-quad2.adoc[]
+include::images/bytefield/rvc-instr-quad2.edn[]
 //include::images/bytefield/rvc-instr-quad2.png[]

src/machine.adoc

@@ -251,7 +251,7 @@ implementation.
 //image::png/mvendorid.png[align="center"]
 
 .Vendor ID register (`mvendorid`)
-include::images/bytefield/mvendorid.adoc[]
+include::images/bytefield/mvendorid.edn[]
 
 JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte
 continuation codes `0x7f`, terminated by a one-byte ID not equal to
@@ -286,7 +286,7 @@ uniquely identify the type of hart microarchitecture that is
 implemented.
 
 .Machine Architecture ID (`marchid`) register 
-include::images/bytefield/marchid.adoc[]
+include::images/bytefield/marchid.edn[]
 
 Open-source project architecture IDs are allocated globally by RISC-V
 International, and have non-zero architecture IDs with a zero
@@ -324,7 +324,7 @@ field is not implemented. The Implementation value should reflect the
 design of the RISC-V processor itself and not any surrounding system.
 
 .Machine Implementation ID (`mimpid`) register 
-include::images/bytefield/mimpid.adoc[]
+include::images/bytefield/mimpid.edn[]
 
 [NOTE]
 ====
@@ -346,7 +346,7 @@ must have a hart ID of zero. Hart IDs must be unique within the
 execution environment.
 
 .Hart ID (`mhartid`) register 
-include::images/bytefield/mhartid.adoc[]
+include::images/bytefield/mhartid.edn[]
 
 [NOTE]
 ====
@@ -1170,7 +1170,7 @@ and a vector mode (MODE).
 
 
 .Encoding of mtvec MODE field.
-include::images/bytefield/mtvec.adoc[]
+include::images/bytefield/mtvec.edn[]
 
 The `mtvec` register must always be implemented, but can contain a
 read-only value. If `mtvec` is writable, the set of values the register
@@ -1298,7 +1298,7 @@ is clear, STIs can be taken in any mode and regardless of current mode
 will transfer control to M-mode.
 
 .Machine Exception Delegation (`medeleg`) register.
-include::images/bytefield/medeleg.adoc[]
+include::images/bytefield/medeleg.edn[]
 
 `medeleg` has a bit position allocated for every synchronous exception
 shown in <<mcauses>>, with the index of the
@@ -1311,7 +1311,7 @@ that aliases bits 63:32 of `medeleg`.
 The `medelegh` register does not exist when XLEN=64.
 
 .Machine Interrupt Delegation (`mideleg`) Register.
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 `mideleg` holds trap delegation bits for individual interrupts, with the
 layout of bits matching those in the `mip` register (i.e., STIP
@@ -1337,10 +1337,10 @@ NOTE: Interrupts designated for platform use may be designated for custom use
 at the platform's discretion.
 
 .Machine Interrupt-Pending (`mip`) register.
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 .Machine Interrupt-Enable (`mie`) register
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 An interrupt _i_ will trap to M-mode (causing the privilege mode to
 change to M-mode) if all of the following are true: (a) either the
@@ -1374,11 +1374,11 @@ formatted as shown in <<mipreg-standard>> and <<miereg-standard>> respectively.
 
 [[mipreg-standard]]
 .Standard portion (bits 15:0) of `mip`.
-include::images/bytefield/mipreg-standard.adoc[]
+include::images/bytefield/mipreg-standard.edn[]
 
 [[miereg-standard]]
 .Standard portion (bits 15:0) of `mie`.
-include::images/bytefield/miereg-standard.adoc[]
+include::images/bytefield/miereg-standard.edn[]
 
 [NOTE]
 ====
@@ -1529,7 +1529,7 @@ implementation is to make both the counter and its corresponding event
 selector be read-only 0.
 
 .Hardware performance monitor counters.
-include::images/bytefield/hpmevents.adoc[]
+include::images/bytefield/hpmevents.edn[]
 
 The `mhpmcounters` are *WARL* registers that support up to 64 bits of
 precision on RV32 and RV64.
@@ -1549,7 +1549,7 @@ controls the availability of the hardware performance-monitoring
 counters to the next-lower privileged mode.
 
 .Counter-enable (`mcounteren`) register.
-include::images/bytefield/counteren.adoc[]
+include::images/bytefield/counteren.edn[]
 
 The settings in this register only control accessibility. The act of
 reading or writing this register does not affect the underlying
@@ -1597,7 +1597,7 @@ executing in a less-privileged mode. In harts without U-mode, the
 ==== Machine Counter-Inhibit (`mcountinhibit`) Register 
 
 .Counter-inhibit `mcountinhibit` register
-include::images/bytefield/counterinh.adoc[]
+include::images/bytefield/counterinh.edn[]
 
 The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that
 controls which of the hardware performance-monitoring counters
@@ -1636,7 +1636,7 @@ machine-mode hart-local context space and swapped with a user register
 upon entry to an M-mode trap handler.
 
 .Machine-mode scratch register.
-include::images/bytefield/mscratch.adoc[]
+include::images/bytefield/mscratch.edn[]
 
 [NOTE]
 ====
@@ -1689,7 +1689,7 @@ though it may be explicitly written by software.
 
 [[mepcreg]]
 .Machine exception program counter register.
-include::images/bytefield/mepcreg.adoc[]
+include::images/bytefield/mepcreg.edn[]
 
 [[mcause]]
 ==== Machine Cause (`mcause`) Register 
@@ -1708,7 +1708,7 @@ the possible machine-level exception codes. The Exception Code is a
 
 [[mcausereg]]
 .Machine Cause (`mcause`) register.
-include::images/bytefield/mcausereg.adoc[]
+include::images/bytefield/mcausereg.edn[]
 
 Note that load and load-reserved instructions generate load exceptions,
 whereas store, store-conditional, and AMO instructions generate
@@ -1986,7 +1986,7 @@ particularly those with hardware page-table walkers.
 
 [[mtvalreg]]
 .Machine Trap Value (`mtval`) register.
-include::images/bytefield/mtvalreg.adoc[]
+include::images/bytefield/mtvalreg.edn[]
 
 
 If `mtval` is written with a nonzero value when a misaligned load or
@@ -2067,7 +2067,7 @@ and their configuration.
 
 [[mconfigptrreg]]
 .Machine Configuration Pointer (`mconfigptr`) register.
-include::images/bytefield/mconfigptrreg.adoc[]
+include::images/bytefield/mconfigptrreg.edn[]
 
 
 The pointer alignment in bits must be no smaller than MXLEN:
@@ -2274,10 +2274,10 @@ writing `mtimecmp`). The interrupt will only be taken if interrupts are
 enabled and the MTIE bit is set in the `mie` register.
 
 .Machine time register (memory-mapped control register).
-include::images/bytefield/mtime.adoc[]
+include::images/bytefield/mtime.edn[]
 
 .Machine time compare register (memory-mapped control register).
-include::images/bytefield/mtimecmp.adoc[]
+include::images/bytefield/mtimecmp.edn[]
 
 [NOTE]
 ====
@@ -2502,7 +2502,7 @@ minimum required privilege mode, as do other SYSTEM instructions.
 
 [[customsys]]
 .SYSTEM instruction encodings designated for custom use.
-include::images/bytefield/cust-sys-instr.adoc[]
+include::images/bytefield/cust-sys-instr.edn[]
 
 [[reset]]
 === Reset
@@ -3054,11 +3054,11 @@ entries 8-11 appear in `pmpcfg2`[31:0] for both RV32 and RV64.
 
 [[pmpcfg-rv32]]
 .RV32 PMP configuration CSR layout.
-include::images/bytefield/pmp-rv32.adoc[]
+include::images/bytefield/pmp-rv32.edn[]
 
 [[pmpcfg-rv64]]
 .RV64 PMP configuration CSR layout.
-include::images/bytefield/pmp-rv64.adoc[]
+include::images/bytefield/pmp-rv64.edn[]
 
 
 The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`. Each
@@ -3082,11 +3082,11 @@ the same limit.
 
 [[pmpaddr-rv32]]
 .PMP address register format, RV32.
-include::images/bytefield/pmpaddr-rv32.adoc[]
+include::images/bytefield/pmpaddr-rv32.edn[]
 
 [[pmpaddr-rv64]]
 .PMP address register format, RV64.
-include::images/bytefield/pmpaddr-rv64.adoc[]
+include::images/bytefield/pmpaddr-rv64.edn[]
 
 <<pmpcfg>> shows the layout of a PMP configuration
 register. The R, W, and X bits, when set, indicate that the PMP entry
@@ -3096,7 +3096,7 @@ W, and X fields form a collective *WARL* field for which the combinations with R
 
 [[pmpcfg]]
 .PMP configuration register format.
-include::images/bytefield/pmpcfg.adoc[]
+include::images/bytefield/pmpcfg.edn[]
 
 
 Attempting to fetch an instruction from a PMP region that does not have

src/rnmi.adoc

@@ -36,7 +36,7 @@ This proposal adds additional M-mode CSRs to enable a resumable
 non-maskable interrupt (RNMI).
 
 .Resumable NMI scratch register `mnscratch`
-include::images/bytefield/mnscratch.adoc[]
+include::images/bytefield/mnscratch.edn[]
 
 The `mnscratch` CSR holds an MXLEN-bit read-write register which enables
 the NMI trap handler to save and restore the context that was