back.rtlil: infer bit width for instance parameters.

Otherwise, Yosys assumes it is always 32, which is often inappropriate.
rroohhh · Nov 27, 2019 · f8428ff · f8428ff
1 parent 56bb42a
commit f8428ff
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
@@ -128,8 +128,8 @@ def cell(self, kind, name=None, params={}, ports={}, attrs={}, src=""):
                 self._append("    parameter \\{} \"{}\"\n",
                              param, value.translate(self._escape_map))
             elif isinstance(value, int):
-                self._append("    parameter \\{} {:d}\n",
-                             param, value)
+                self._append("    parameter \\{} {}'{:b}\n",
+                             param, bits_for(value), value)
             elif isinstance(value, float):
                 self._append("    parameter real \\{} \"{!r}\"\n",
                              param, value)