Releases · rsd-devel/rsd

Added features from v1.0.0

set-associative cache
cache flush
uncachable memory regions
external interrupt

What's Changed

Fixed wrong format string by @mmxsrup in #3
Added simulation environment for Vivado by @mmxsrup in #2
Fix license information so GitHub detects it correctly by @mithro in #8
Fix errors for synthesis on Vivado 2019.2 by @reo-pon in #11
Fix modport direction and conflict by @dalance in #12
Add Vivado 2019.2 support and Debian on Zedboard support by @msmssm in #13
Correct some typos in RSD_Parser.py by @felixonmars in #14
Add support synthesizing RSD on vivado only by @reo-pon in #16
Added loader by @clkbug in #4
Add uncachable memory access support by @msmssm in #17
Added return statement to GetCommittedRegisterValue by @odxa20 in #20
Modify Verilator's configuration by @shioyadan in #21
Add a cache flush feature by @msmssm in #22
Add external interrupt by @shioyadan in #23
Fix for latest sim by @shioyadan in #25
Add setassociative dcache tree lru by @shioyadan in #26
Add performance counters by @shioyadan in #27
Improve kanata converter by @shioyadan in #28
Add a feature that easily modifies microarchitectural parameters by @shioyadan in #29
Fix dc configuration by @shioyadan in #46
Fix baremetal loader by @shioyadan in #52
Fix broken Vivado synthesis/simulation in Ubuntu 22.04 by @shioyadan in #54
Fix a bug that causes incorrect recovery if all instructions are flushed when ActiveList is full by @reo-pon in #51
Fix wakeup pipeline by @momorrowz in #55
Fix wakeup pipeline register by @momorrowz in #57
fix: fix a bug of bypassing conditions in integer backend by @momorrowz in #56
fix: fix incorrect description of intPipe & add assert and comments by @momorrowz in #58
fix: fix MSHR-related bugs by @shioyadan in #59
Fix vivado synthesis by @shioyadan in #60
fix: add necessary header include in WakeupPipelineRegister.sv by @shioyadan in #61
docs: update CREDITS.md by @shioyadan in #62