rust-embedded · jonathanpallant · Sep 29, 2025 · Sep 28, 2025
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -38,7 +38,7 @@ jobs:
           rustup target add ${{ matrix.target }}
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }}
+          cargo build --target ${{ matrix.target }} --features "serde, defmt"
           cargo build --target ${{ matrix.target }} --no-default-features
 
   build-versatileab:

diff --git a/cortex-ar/CHANGELOG.md b/cortex-ar/CHANGELOG.md
@@ -17,6 +17,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   maintenance by MVA (specific address).
 - Added new  `L1Section::set_section_attrs` and `L1Section::section_attrs` method. Also added
   low-level `L1Section::new_with_addr_upper_bits_and_attrs` constructor.
+- optional `serde` derives behind a `serde` feature gate
+- lots of missing `Debug`, `Copy`, `Clone`, `defmt::Format` derives.
 
 ### Changed
 

diff --git a/cortex-ar/Cargo.toml b/cortex-ar/Cargo.toml
@@ -26,11 +26,12 @@ version = "0.2.0"
 
 [dependencies]
 arbitrary-int = "2"
-bitbybit = "1.3.3"
+bitbybit = "1.4"
 num_enum = { version = "0.7", default-features = false }
 critical-section = {version = "1.2.0", features = ["restore-state-u8"], optional = true}
 thiserror = { version = "2", default-features = false }
-defmt = {version = "1", optional = true}
+defmt = { version = "1", optional = true }
+serde = { version = "1", features = ["derive"], default-features = false, optional = true }
 
 [build-dependencies]
 arm-targets = {version = "0.2.0", path = "../arm-targets"}
@@ -44,6 +45,7 @@ critical-section-single-core = ["critical-section"]
 critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
 defmt = ["dep:defmt", "arbitrary-int/defmt"]
+serde = ["dep:serde", "arbitrary-int/serde"]
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]
diff --git a/cortex-ar/src/mmu.rs b/cortex-ar/src/mmu.rs
@@ -2,11 +2,13 @@ use arbitrary_int::{u12, u2, u3, u4};
 
 #[derive(Debug, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[error("invalid L1 entry type {0:?}")]
 pub struct InvalidL1EntryType(pub L1EntryType);
 
 #[bitbybit::bitenum(u3, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum AccessPermissions {
     PermissionFault = 0b000,
@@ -40,6 +42,7 @@ impl AccessPermissions {
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum L1EntryType {
@@ -60,6 +63,7 @@ pub enum L1EntryType {
 /// of the B, C, and TEX bits.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct MemoryRegionAttributesRaw {
     /// TEX bits
     type_extensions: u3,
@@ -80,6 +84,7 @@ impl MemoryRegionAttributesRaw {
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug)]
 pub enum CacheableMemoryAttribute {
     NonCacheable = 0b00,
@@ -90,6 +95,7 @@ pub enum CacheableMemoryAttribute {
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub enum MemoryRegionAttributes {
     StronglyOrdered,
     ShareableDevice,
@@ -142,6 +148,7 @@ impl MemoryRegionAttributes {
 /// Individual section attributes for a L1 section.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct SectionAttributes {
     /// NG bit
     pub non_global: bool,
@@ -205,7 +212,8 @@ impl SectionAttributes {
 ///
 /// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the ARMv7-A and ArmV7-R
 /// architecture reference manual p.1323 specify these attributes in more detail.
-#[bitbybit::bitfield(u32, default = 0x00)]
+#[bitbybit::bitfield(u32, default = 0, defmt_fields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(PartialEq, Eq)]
 pub struct L1Section {
     /// Section base address upper bits.

diff --git a/cortex-ar/src/pmsav7.rs b/cortex-ar/src/pmsav7.rs
@@ -13,6 +13,7 @@ pub use register::drsr::RegionSize;
 
 /// Ways this API can fail
 #[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     /// Found too many regions
     TooManyRegions,

diff --git a/cortex-ar/src/register/actlr.rs b/cortex-ar/src/register/actlr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ACTLR (*Auxiliary Control Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr(pub u32);
 impl SysReg for Actlr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/actlr2.rs b/cortex-ar/src/register/actlr2.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ACTLR2 (*Auxiliary Control Register 2*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr2(pub u32);
 impl SysReg for Actlr2 {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/adfsr.rs b/cortex-ar/src/register/adfsr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// ADFSR (*Auxiliary Data Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Adfsr(pub u32);
 impl SysReg for Adfsr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/aidr.rs b/cortex-ar/src/register/aidr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead};
 
 /// AIDR (*Auxiliary ID Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aidr(pub u32);
 impl SysReg for Aidr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/aifsr.rs b/cortex-ar/src/register/aifsr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// AIFSR (*Auxiliary Instruction Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aifsr(pub u32);
 impl SysReg for Aifsr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/amair0.rs b/cortex-ar/src/register/amair0.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair0(pub u32);
 impl SysReg for Amair0 {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/amair1.rs b/cortex-ar/src/register/amair1.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair1(pub u32);
 impl SysReg for Amair1 {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/cntfrq.rs b/cortex-ar/src/register/armv8r/cntfrq.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTFRQ (*Counter-timer Frequency Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cntfrq(pub u32);
 impl SysReg for Cntfrq {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/cnthctl.rs b/cortex-ar/src/register/armv8r/cnthctl.rs
@@ -5,7 +5,8 @@ use arbitrary_int::u4;
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTHCTL (*Hyp Counter-timer Control Register*)
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cnthctl {
     #[bits(19..=19, rw)]
     cntpmask: bool,

diff --git a/cortex-ar/src/register/armv8r/cnthp_ctl.rs b/cortex-ar/src/register/armv8r/cnthp_ctl.rs
@@ -3,19 +3,20 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CnthpCtl {
     /// The status of the timer interrupt.
-    #[bits(2..=2, r)]
+    #[bit(2, r)]
     istatus: bool,
     /// Timer interrupt mask bit.
     ///
     /// * true: masked
     /// * false: not masked
-    #[bits(1..=1, rw)]
+    #[bit(1, rw)]
     imask: bool,
     /// Enables the timer.
-    #[bits(0..=0, rw)]
+    #[bit(0, rw)]
     enable: bool,
 }
 

diff --git a/cortex-ar/src/register/armv8r/cnthp_cval.rs b/cortex-ar/src/register/armv8r/cnthp_cval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CnthpCval(pub u64);
 
 impl SysReg64 for CnthpCval {

diff --git a/cortex-ar/src/register/armv8r/cnthp_tval.rs b/cortex-ar/src/register/armv8r/cnthp_tval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTHP_TVAL (*Hyp Physical Counter-timer TimerValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CnthpTval(pub u32);
 
 impl SysReg for CnthpTval {

diff --git a/cortex-ar/src/register/armv8r/cntkctl.rs b/cortex-ar/src/register/armv8r/cntkctl.rs
@@ -5,7 +5,8 @@ use arbitrary_int::u4;
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTKCTL (*Counter-timer Kernel Control Register*)
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cntkctl {
     /// Controls whether the physical timer registers are accessible from EL0
     /// modes.

diff --git a/cortex-ar/src/register/armv8r/cntp_ctl.rs b/cortex-ar/src/register/armv8r/cntp_ctl.rs
@@ -3,7 +3,8 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTP_CTL (*Physical Counter-timer Control Register*)
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntpCtl {
     /// The status of the timer interrupt.
     #[bits(2..=2, r)]

diff --git a/cortex-ar/src/register/armv8r/cntp_cval.rs b/cortex-ar/src/register/armv8r/cntp_cval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntpCval(pub u64);
 
 impl SysReg64 for CntpCval {

diff --git a/cortex-ar/src/register/armv8r/cntp_tval.rs b/cortex-ar/src/register/armv8r/cntp_tval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntpTval(pub u32);
 impl SysReg for CntpTval {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/cntpct.rs b/cortex-ar/src/register/armv8r/cntpct.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64};
 
 /// CNTPCT (*Physical Counter-timer Count Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntPct(pub u64);
 
 impl SysReg64 for CntPct {

diff --git a/cortex-ar/src/register/armv8r/cntv_ctl.rs b/cortex-ar/src/register/armv8r/cntv_ctl.rs
@@ -3,7 +3,8 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTV_CTL (*Virtual Counter-timer Control Register*)
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, defmt_bitfields(feature = "defmt"))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntvCtl {
     /// The status of the timer interrupt.
     #[bits(2..=2, r)]

diff --git a/cortex-ar/src/register/armv8r/cntv_cval.rs b/cortex-ar/src/register/armv8r/cntv_cval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTV_CVAL (*Virtual Counter-timer CompareValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntvCval(pub u64);
 
 impl SysReg64 for CntvCval {

diff --git a/cortex-ar/src/register/armv8r/cntv_tval.rs b/cortex-ar/src/register/armv8r/cntv_tval.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntvTval(pub u32);
 impl SysReg for CntvTval {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/cntvct.rs b/cortex-ar/src/register/armv8r/cntvct.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64};
 
 /// CNTVCT (*Virtual Counter-timer Count Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntVct(pub u64);
 
 impl SysReg64 for CntVct {

diff --git a/cortex-ar/src/register/armv8r/cntvoff.rs b/cortex-ar/src/register/armv8r/cntvoff.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTVOFF (*Virtual Counter-timer Offset Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntVoff(pub u64);
 
 impl SysReg64 for CntVoff {

diff --git a/cortex-ar/src/register/armv8r/hacr.rs b/cortex-ar/src/register/armv8r/hacr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HACR (*Hyp Auxiliary Configuration Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hacr(pub u32);
 impl SysReg for Hacr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/hactlr.rs b/cortex-ar/src/register/armv8r/hactlr.rs
@@ -4,6 +4,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HACTRL (*Hyp Auxiliary Control Register*)
 #[bitbybit::bitfield(u32)]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hactlr {
     /// Controls access to IMP_TESTR1 at EL0 and EL1
     #[bits(15..=15, rw)]

diff --git a/cortex-ar/src/register/armv8r/hactlr2.rs b/cortex-ar/src/register/armv8r/hactlr2.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HACTLR2 (*Hyp Auxiliary Control Register 2*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hactlr2(pub u32);
 impl SysReg for Hactlr2 {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/hadfsr.rs b/cortex-ar/src/register/armv8r/hadfsr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HADFSR (*Hyp Auxiliary Data Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hadfsr(pub u32);
 impl SysReg for Hadfsr {
     const CP: u32 = 15;

diff --git a/cortex-ar/src/register/armv8r/haifsr.rs b/cortex-ar/src/register/armv8r/haifsr.rs
@@ -3,6 +3,9 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HAIFSR (*Hyp Auxiliary Instruction Fault Status Register*)
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Haifsr(pub u32);
 impl SysReg for Haifsr {
     const CP: u32 = 15;