fix(instructions): allow unused_unsafe for cpuid

src/instructions/random.rs

@@ -10,6 +10,7 @@ impl RdRand {
     pub fn new() -> Option<Self> {
         // RDRAND support indicated by CPUID page 01h, ecx bit 30
         // https://en.wikipedia.org/wiki/RdRand#Overview
+        #[allow(unused_unsafe)]
         let cpuid = unsafe { core::arch::x86_64::__cpuid(0x1) };
         if cpuid.ecx & (1 << 30) != 0 {
             Some(RdRand(()))

src/instructions/smap.rs

@@ -35,6 +35,7 @@ impl Smap {
     /// CR4.
     pub fn new() -> Option<Self> {
         // Check if the CPU supports `stac` and `clac`.
+        #[allow(unused_unsafe)]
         let cpuid = unsafe { core::arch::x86_64::__cpuid(7) };
         if cpuid.ebx.get_bit(20) {
             Some(Self(()))

src/instructions/tlb.rs

@@ -160,6 +160,7 @@ impl Invlpgb {
         assert_eq!(cs.rpl(), PrivilegeLevel::Ring0);
 
         // Check if the `INVLPGB` and `TLBSYNC` instruction are supported.
+        #[allow(unused_unsafe)]
         let cpuid = unsafe { core::arch::x86_64::__cpuid(0x8000_0008) };
         if !cpuid.ebx.get_bit(3) {
             return None;
@@ -169,6 +170,7 @@ impl Invlpgb {
         let invlpgb_count_max = cpuid.edx.get_bits(0..=15) as u16;
 
         // Figure out the number of supported ASIDs.
+        #[allow(unused_unsafe)]
         let cpuid = unsafe { core::arch::x86_64::__cpuid(0x8000_000a) };
         let nasid = cpuid.ebx;