SoC design for Cortex M0
Replace a SPARC Leon3 processor with ARM’s Cortex M0 while still using an existing SoC infrastructure.
Since the two processors use different type of interface (Leon3 with AHB interface and Cortex M0 with AHB lite), a bridge must be made to “translate” the given instructions of Cortex M0 to the AMBA bus. ModelSim and Xilinx ISE are used for design and simulation.
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VHDL implementation of an AHB bridge to connect AHB lite to AMBA bus.
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