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README
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Pipeline PROCESSOR:
Author: 2016eeb1087(sanket Nyayadhish)
Date: 22/12/2017
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command: ./assembler program.asm Input_Memory
iverilog -o Test_pipeline.vvp Test_pipeline.v
vvp Test_pipeline.vvp
gtkwave Pipeline.vcd //(for analysis.)
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* I Designed a pipeline Processor in Pipeline.v and included this file in Test_pipeline.v.
* I Created a instance of Pipeline(P) in test file an also created instances of
IF (IF1) ,OF (OF1) , EX (EX1) , MA (MA1) , WB (WB1) , Register_File (RF1) , Memory (M1)
ALU (ALU1),IF_OF(PR1),OF_EX(PR2),EX_MA(PR3),MA_WB(PR4) in Pipeline.v.
* The Assembly Code is in "program.asm" file.
* The Hex Instructions are in "Input_Memory" file.
* The output i.e. updated memory and updated registers values are stored in a "Updated_data" file.
*Note: The Simulation time is constant(`td) and can be changed from the Test_processor.v.
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