Pipelined Processer

Description

It is 5 stage pipeline processor without forwarding path and data lock unit.
The 5 stages are
1. Instruction fetch (IF)
2. Operand fetch (OF)
3. Execute (EX)
4. Memory Access (MA)
5. Write Back (WB)
It has 4 Pipeline registers. All are negetive edge clock triggered.
1. PR1 (IF_OF)
2. PR2 (OF_EX)
3. PR3 (EX_MA)
4. PR4 (MA_WB)

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
500px-Pipeline_MIPS.png		500px-Pipeline_MIPS.png
68747470733a2f2f756e646572677261642e6878696e672e6d652f56453337302f53696e676c652b4379636c652b536368656d61746963732e706e673f782d736f757263653d676974687562.png		68747470733a2f2f756e646572677261642e6878696e672e6d652f56453337302f53696e676c652b4379636c652b536368656d61746963732e706e673f782d736f757263653d676974687562.png
Alu.v		Alu.v
Control.v		Control.v
EX.v		EX.v
EX_MA.v		EX_MA.v
IF.v		IF.v
IF_OF.v		IF_OF.v
Input_Memory		Input_Memory
MA.v		MA.v
MA_WB.v		MA_WB.v
Memory.v		Memory.v
OF.v		OF.v
OF_EX.v		OF_EX.v
Pipeline.v		Pipeline.v
Pipeline.vcd		Pipeline.vcd
README		README
README.md		README.md
Register_File.v		Register_File.v
Test_pipeline.v		Test_pipeline.v
Test_pipeline.vvp		Test_pipeline.vvp
Updated_data		Updated_data
WB.v		WB.v
assembler		assembler
program.asm		program.asm