fixbugs

sarchlab · Sep 16, 2024 · 12b9667 · 12b9667
1 parent 49d973a
commit 12b9667
Show file tree

Hide file tree

Showing 3 changed files with 13 additions and 8 deletions.
diff --git a/mem/idealmemcontroller/builder.go b/mem/idealmemcontroller/builder.go
@@ -91,11 +91,12 @@ func (b Builder) Build(
 		Latency: b.latency,
 		width:   b.width,
 		ctrlState: mem.Pause{
-			Enable:  false,
+			Enable:  true,
 			Drain:   false,
 			Flush:   false,
 			Invalid: false,
 		},
+		state: "enable",
 	}
 
 	c.TickingComponent = sim.NewTickingComponent(name, b.engine, b.freq, c)

diff --git a/mem/idealmemcontroller/comp.go b/mem/idealmemcontroller/comp.go
@@ -57,7 +57,6 @@ type Comp struct {
 func (c *Comp) Tick() bool {
 	madeProgress := false
 
-	// get ctrl msg from ctrl port
 	madeProgress = c.handleCtrlSignals() || madeProgress
 	madeProgress = c.updateInflightBuffer() || madeProgress
 	madeProgress = c.handleBehavior() || madeProgress
@@ -109,11 +108,15 @@ func (c *Comp) Handle(e sim.Event) error {
 
 func (c *Comp) handleCtrlSignals() (madeProgress bool) {
 	for {
-		msg := c.CtrlPort.RetrieveIncoming()
+		msg := c.CtrlPort.PeekIncoming()
 		if msg == nil {
 			return madeProgress
 		}
 
+		if c.state == "drain" {
+			return madeProgress
+		}
+
 		signalMsg := msg.(*mem.ControlMsg)
 
 		if c.handleInvalidOrFlushSignal(signalMsg) {
@@ -131,6 +134,8 @@ func (c *Comp) handleCtrlSignals() (madeProgress bool) {
 		if c.handlePauseSignal(signalMsg) {
 			return true
 		}
+
+		c.CtrlPort.RetrieveIncoming()
 	}
 }
 
@@ -193,12 +198,13 @@ func (c *Comp) handleInflightMemReqs() bool {
 }
 
 func (c *Comp) handleMemReqs() bool {
-	msg := c.inflightbuffer[0]
-	c.inflightbuffer = c.inflightbuffer[1:]
-	if msg == nil {
+	if len(c.inflightbuffer) == 0 {
 		return false
 	}
 
+	msg := c.inflightbuffer[0]
+	c.inflightbuffer = c.inflightbuffer[1:]
+
 	tracing.TraceReqReceive(msg, c)
 
 	switch msg := msg.(type) {

diff --git a/mem/idealmemcontroller/idealmemcontroller_test.go b/mem/idealmemcontroller/idealmemcontroller_test.go
@@ -49,7 +49,6 @@ var _ = Describe("Ideal Memory Controller", func() {
 			Build()
 		port.EXPECT().RetrieveIncoming().Return(readReq)
 		ctrlPort.EXPECT().PeekIncoming().Return(nil)
-		ctrlPort.EXPECT().RetrieveIncoming().Return(nil)
 		engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
 		engine.EXPECT().
@@ -69,7 +68,6 @@ var _ = Describe("Ideal Memory Controller", func() {
 			Build()
 		port.EXPECT().RetrieveIncoming().Return(writeReq)
 		ctrlPort.EXPECT().PeekIncoming().Return(nil)
-		ctrlPort.EXPECT().RetrieveIncoming().Return(nil)
 		engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
 		engine.EXPECT().