Fix

scorbetta · Mar 27, 2024 · a7392e4 · a7392e4
1 parent 36ffb44
commit a7392e4
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Showing 3 changed files with 24 additions and 27 deletions.
diff --git a/docs/info.md b/docs/info.md
@@ -77,18 +77,14 @@ The top-level `tt_um_scorbetta_goa` adheres to the following pinout:
 | PIN | DIRECTION | ROLE |
 |-|-|-|
 | `ui_in[0]` | input | Core clock, generated by the FPGA |
-| `ui_in[1]` | input | Active-low core reset |
-| `ui_in[2]` | input | `SCI_CSN` |
-| `ui_in[3]` | input | `SCI_REQ` |
-| `ui_in[4]` | input | Load value in |
-| `ui_in[5]` | input | Value in |
-| `ui_in[6]` | input | Shift result out |
-| `ui_in[7]` | input | Neuron trigger |
+| `ui_in[1]` | input | `SCI_CSN` |
+| `ui_in[2]` | input | `SCI_REQ` |
+| `ui_in[7:3]` | input | Unused |
 | `uo_out[0]` | output | `SCI_RESP` |
 | `uo_out[1]` | output | `SCI_ACK` |
-| `uo_out[2]` | output | Result out |
-| `uo_out[3]` | output | Neuron ready |
-| `uo_out[4]` | output | Neuron done |
+| `uo_out[2]` | output | Debug counter [2] |
+| `uo_out[3]` | output | Debug counter [3] |
+| `uo_out[4]` | output | Debug counter [4] |
 | `uo_out[5]` | output | Debug counter [5] |
 | `uo_out[6]` | output | Debug counter [6] |
 | `uo_out[7]` | output | Debug counter [7] |

diff --git a/info.yaml b/info.yaml
@@ -23,6 +23,7 @@ project:
     - "FIXED_POINT_ACT_FUN.v"
     - "RW_REG.v"
     - "RO_REG.v"
+    - "DELTA_REG.v"
     - "REGPOOL.v"
     - "D_FF_EN.v"
     - "PISO_BUFFER.v"
@@ -39,23 +40,23 @@ project:
 pinout:
   # Inputs
   ui[0]: "FPGA clock"
-  ui[1]: "FPGA reset"
-  ui[2]: "SCI_CSN"
-  ui[3]: "SCI_REQ"
-  ui[4]: "Input value load-in"
-  ui[5]: "Input value"
-  ui[6]: "Output value shift-out"
-  ui[7]: "Neuron trigger"
+  ui[1]: "SCI_CSN"
+  ui[2]: "SCI_REQ"
+  ui[3]: ""
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
 
   # Outputs
   uo[0]: "SCI_RESP"
   uo[1]: "SCI_ACK"
-  uo[2]: "Output value"
-  uo[3]: "Neuron ready"
-  uo[4]: "Neuron done"
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[2]: "10-bit counter value [4]"
+  uo[3]: "10-bit counter value [5]"
+  uo[4]: "10-bit counter value [6]"
+  uo[5]: "10-bit counter value [7]"
+  uo[6]: "10-bit counter value [8]"
+  uo[7]: "10-bit counter value [9]"
 
   # Bidirectional pins
   uio[0]: ""

diff --git a/src/tt_um_scorbetta_goa.v b/src/tt_um_scorbetta_goa.v
@@ -22,11 +22,11 @@ module tt_um_scorbetta_goa
     input wire          rst_n // reset_n - low to reset
 );
 
-    wire [11:0] counter;
+    wire [9:0] counter;
 
     // Use main clock to check power
     COUNTER #(
-        .WIDTH  (12)
+        .WIDTH  (10)
     )
     COUNTER (
         .CLK        (clk),
@@ -36,8 +36,8 @@ module tt_um_scorbetta_goa
         .OVERFLOW   () // Unused
     );
 
-    // Check three MSBs
-    assign uo_out[7:2] = counter[7:2];
+    // Check 6 MSBs
+    assign uo_out[7:2] = counter[9:4];
 
     // User design uses a custom clock, generated by remote FPGA
     NEURON_WRAPPER NEURON_WRAPPER (