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Assignment 7, Digital Logic Design Lab, Spring 2021, IIT Bombay

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CS 254: Assignment 7

Team Members:
1. Devansh Jain  (190100044)
2. Harshit Varma (190100055)

File Descriptions:

Q1:
    RLE.vhd                         : Contains the Run Length Encoder using behavorial coding
    ASCII_Read_test.vhd             : Modified Testbench for RLE.vhd
    input.txt                       : Input Testcase
    output.txt                      : Output of Testcase
    waveform_1.png & waveform_2.png : Waveforms of the simulation
    report.pdf                      : Description of implementation
    

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Assignment 7, Digital Logic Design Lab, Spring 2021, IIT Bombay

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