My lousy attempt at implementing the great Ben Eater's 8-bit CPU on an FPGA
I'm using the Mimas V2 board,
which features a Spartan 6, and I'm using Xilinx's ISE WebPack 14.7, and I'm flashing with
MimasV2Config.py through the serial console (/dev/ttyACM0 in my case).
| Mnemonic | Binary coding | Meaning |
|---|---|---|
| NOP | 0000_xxxx |
Do nothing |
| LDA | 0001_nnnn |
Load 8-bit value from memory at address nnnn into register A |
| ADD | 0010_nnnn |
Load 8-bit value from memory at address nnnn into register B, then add A and B and store result in A |
| SUB | 0011_nnnn |
Load 8-bit value from memory at address nnnn into register B, subtract B from A and store result in A |
| JMP | 0110_nnnn |
Jump to address nnnn |
| JC | 0111_nnnn |
Jump to address nnnn if the result of a ALU operation resulted in overflow (carry) |
| JZ | 1000_nnnn |
Jump to address nnnn if the result of a ALU operation resulted in value 0 |
| LDI | 0101_nnnn |
Load immediate, 4-bit value nnnn into register A |
| OUT | 1110_xxxx |
Push the current bus's state into the OUT register (on my board it goes onto the LEDs) |
| HLT | 1111_xxxx |
Halts the CPU (cannot recover, except by powercycling) |