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This project deals with the hardware design building for ML models like ViT and its verification on FPGA Boards

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Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
ALU.v.txt		ALU.v.txt
ALU_Tb.v.txt		ALU_Tb.v.txt
RAM.v		RAM.v
README.md		README.md
Ram_Tb.v		Ram_Tb.v
array_addition.cpp		array_addition.cpp
array_addition.h		array_addition.h
array_addition_tb.cpp		array_addition_tb.cpp
code.ipynb		code.ipynb
code_file.ipynb		code_file.ipynb
nn_mnist.cpp		nn_mnist.cpp
nn_mnist_test.cpp		nn_mnist_test.cpp

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FPGA_ML_Accelerator

Contributors: Shikhar Dave and Mahek Vanjani

This project is based on the implementation of ML models on the FPGA boards. We have used kintex-7 Genesys 2 and PYNQ z2 Board.

Click here for Pynq Basic Documentaion by us

We will be using Vitis HLS 2023 version for making the .bit and .tcl file for the model specific hardware design.

Resources for ViT study -

The first project we did in vitis HLS was array addition. The cpp file for source and testbench have been added along with the header file.

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This project deals with the hardware design building for ML models like ViT and its verification on FPGA Boards

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