RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_fv.c

@@ -0,0 +1,189 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+/*
+** test_sf_vc_fv_se_u16mf4:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16mf4(const int bit_field26, const int bit_field11_7, vuint16mf4_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16mf4(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16mf2:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16mf2(const int bit_field26, const int bit_field11_7, vuint16mf2_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16mf2(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16m1:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16m1(const int bit_field26, const int bit_field11_7, vuint16m1_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16m1(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16m2:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16m2(const int bit_field26, const int bit_field11_7, vuint16m2_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16m2(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16m4:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16m4(const int bit_field26, const int bit_field11_7, vuint16m4_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16m4(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u16m8:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u16m8(const int bit_field26, const int bit_field11_7, vuint16m8_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u16m8(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u32mf2:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u32mf2(const int bit_field26, const int bit_field11_7, vuint32mf2_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u32mf2(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u32m1:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u32m1(const int bit_field26, const int bit_field11_7, vuint32m1_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u32m1(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u32m2:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u32m2(const int bit_field26, const int bit_field11_7, vuint32m2_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u32m2(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u32m4:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u32m4(const int bit_field26, const int bit_field11_7, vuint32m4_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u32m4(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u32m8:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u32m8(const int bit_field26, const int bit_field11_7, vuint32m8_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u32m8(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u64m1:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u64m1(const int bit_field26, const int bit_field11_7, vuint64m1_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u64m1(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u64m2:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u64m2(const int bit_field26, const int bit_field11_7, vuint64m2_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u64m2(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u64m4:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u64m4(const int bit_field26, const int bit_field11_7, vuint64m4_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u64m4(bit_field26, bit_field11_7, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fv_se_u64m8:
+** ...
+** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fv_se_u64m8(const int bit_field26, const int bit_field11_7, vuint64m8_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fv_se_u64m8(bit_field26, bit_field11_7, vs2, fs1, vl);
+}

gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_fvv.c

@@ -0,0 +1,190 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+
+/*
+** test_sf_vc_fvv_se_u16mf4:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16mf4(const int bit_field26, vuint16mf4_t vd, vuint16mf4_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16mf4(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u16mf2:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16mf2(const int bit_field26, vuint16mf2_t vd, vuint16mf2_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16mf2(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u16m1:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16m1(const int bit_field26, vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16m1(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u16m2:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16m2(const int bit_field26, vuint16m2_t vd, vuint16m2_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16m2(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u16m4:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16m4(const int bit_field26, vuint16m4_t vd, vuint16m4_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16m4(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u16m8:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u16m8(const int bit_field26, vuint16m8_t vd, vuint16m8_t vs2, float16_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u16m8(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32mf2:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u32mf2(const int bit_field26, vuint32mf2_t vd, vuint32mf2_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u32mf2(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m1:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u32m1(const int bit_field26, vuint32m1_t vd, vuint32m1_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u32m1(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m2:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u32m2(const int bit_field26, vuint32m2_t vd, vuint32m2_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u32m2(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m4:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u32m4(const int bit_field26, vuint32m4_t vd, vuint32m4_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u32m4(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u32m8:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u32m8(const int bit_field26, vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u32m8(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u64m1:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u64m1(const int bit_field26, vuint64m1_t vd, vuint64m1_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u64m1(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u64m2:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u64m2(const int bit_field26, vuint64m2_t vd, vuint64m2_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u64m2(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u64m4:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u64m4(const int bit_field26, vuint64m4_t vd, vuint64m4_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u64m4(bit_field26, vd, vs2, fs1, vl);
+}
+
+/*
+** test_sf_vc_fvv_se_u64m8:
+** ...
+** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
+** ...
+*/
+
+void test_sf_vc_fvv_se_u64m8(const int bit_field26, vuint64m8_t vd, vuint64m8_t vs2, float64_t fs1, size_t vl)
+{
+    __riscv_sf_vc_fvv_se_u64m8(bit_field26, vd, vs2, fs1, vl);
+}