update release notes for 2024.2.0 (#230)

CHANGELOG.md

@@ -7,6 +7,43 @@ Changelog](https://keepachangelog.com/en/1.0.0/), and this project
 adheres to [Calendar Versioning](https://calver.org/) with format
 `YYYY.MINOR.MICRO`.
 
+## [2024.2.0]
+
+### Added
+
+- **Architecture**
+  - Multicast NoC for enhanced accelerator P2P communication
+  - Support for token-based DVFS mechanism over the NoC
+  - New NoC domain CSRs
+  - Implementation of BlitzCoin DVFS algorithm
+
+- **ASIC Design**
+  - Pad integration flow (#227)
+  - Clock-strategy selection from GUI (#227)
+  - Automatic generation of top level (#227)
+
+### Improved
+
+- **Architecture**
+  - Flexible P2P commmunication for mismatched burst lengths
+  - Add a CSR for resetting third-party accelerators
+  - Deprecate old DVFS mechansim and cleanup clock hierarchy
+
+- **Accelerator Design Flows**
+  - Stratus HLS: Add ability to synthesize accelerators for inferred tech
+
+- **Infrastructure**
+  - Bump modelsim support to 2023.2 DE
+  - Improve GUI messaging
+
+### Fixed
+
+- **ASIC Design**
+  - Fix multiport handling in memory integration flow (#227)
+
+- **Infrastructure**
+  - Various fixes for new proFPGA xcvu19p board
+
 ## [2024.1.0]
 
 ### Added

CREDITS.md

@@ -23,9 +23,9 @@ repository, including co-authors of portions of code from the first commit.
  - Luca Piccolboni
  - Christian Pilato
 
-### External collaborators
+### Collaborators
 
-The affiliation of external collaborators is reported at the time of their
+The affiliation of collaborators is reported at the time of their
 contribution. Current affiliation may be different.
 
  - Juan E. Contreras (Pacific Northwest National Laboratory)
@@ -35,6 +35,10 @@ contribution. Current affiliation may be different.
  - John-David Wellman (IBM)
  - Jeff Zhang (Harvard University)
  - Zeran Zhu (University of Illinois)
+ - Martin Cochet (IBM)
+ - Erik Loscalzo (Columbia University)
+ - Ajay Vanamali (Columbia University)
+ - Manish Shankar (Columbia University)
 
 
 ### [Contacts](https://esp.cs.columbia.edu/contact/)

LICENSE

@@ -33,7 +33,11 @@
        - Copyright (c) 2011 CERN
 
 
-   4. All source files released in Git submodules are governed by their
+   4. The module `Tile_LDO_Ctrl` contains an adapted version of a PID
+      controller from OpenCores, released with the LGPL license. The file is tagged
+      with the author, license, and link to the original source.
+
+   5. All source files released in Git submodules are governed by their
       respective license(s) in accordance with the credits and license files
       released in each linked repository.
 

README.md

@@ -20,18 +20,18 @@ DMA, distributed interrupt, and run-time coherence selection, that
 hide the complexity of hardware and software integration from the
 accelerator designer.
 
-Currently, ESP supports the integration of multi-core
-[LEON3](https://www.gaisler.com/index.php/downloads/leongrlib)
-processor from GRLIB and single-core
-[Ariane](https://github.com/pulp-platform/ariane) processors from the
-Pulp Platform. LEON3 implements the SPARC V8 32-bits ISA, while Ariane
-implements the RISC-V 64-bits ISA.
+Currently, ESP supports the integration of the
+[LEON3](https://www.gaisler.com/index.php/downloads/leongrlib) processor from
+GRLIB, the [Ariane](https://github.com/pulp-platform/ariane) core from the PULP
+Platform, and the [Ibex](https://github.com/lowRISC/ibex) core from lowRISC.
+LEON3 implements the SPARC V8 32-bit ISA, Ariane implements the RISC-V
+64-bit ISA, and Ibex implements the RISC-V 32-bit ISA.
 
 In addition to processor cores, ESP embeds accelerator design examples
 created with Stratus HLS in SystemC, Vivado HLS in C/C++ and Chisel.
 
 Furthermore, ESP can serve as a platform to integrate third-party IP
-blocks.  For example, ESP integrates the NVIDIA Deep Learning
+blocks. For example, ESP integrates the NVIDIA Deep Learning
 Accelerator [NVDLA](http://nvdla.org/), which can be placed on any ESP
 accelerator tile.
 
@@ -91,5 +91,5 @@ please refer to the READMEs inside each of them for more information.
 ## Stay tuned for the new features under development:
 
    - Dynamic partial reconfiguration SoC flow
-   - New machine learning and cryptography accelerators
    - Expanded support for ASIC design
+   - New platform services for programmable accelerators

rtl/sockets/dvfs/Tile_LDO_Ctrl.v

@@ -1,5 +1,3 @@
-// Copyright (c) 2011-2024 Columbia University, System Level Design Group
-
 /* PID_Ctrl module RTL adapted from OpenCores PID controller
 Link: https://opencores.org/projects/pid_controller
 Author: Zhu Xu