Merge branch 'develop' into testing

.github/workflows/codeql-analysis.yml

@@ -13,12 +13,12 @@ name: "CodeQL"
 
 on:
   push:
-    branches: [ testing, develop, master ]
+    branches: [testing, develop, master]
   pull_request:
     # The branches below must be a subset of the branches above
-    branches: [ testing, develop ]
+    branches: [testing, develop]
   schedule:
-    - cron: '00 20 * * 1'
+    - cron: "00 20 * * 1"
 
 jobs:
   analyze:
@@ -28,7 +28,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        language: [ 'cpp' ]
+        language: ["cpp"]
         # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ]
         # Learn more:
         # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed
@@ -41,7 +41,7 @@ jobs:
 
       # Initializes the CodeQL tools for scanning.
       - name: Initialize CodeQL
-        uses: github/codeql-action/init@v1
+        uses: github/codeql-action/init@v2
         with:
           languages: ${{ matrix.language }}
           # If you wish to specify custom queries, you can do so here or in a config file.
@@ -52,7 +52,7 @@ jobs:
       # Autobuild attempts to build any compiled languages  (C/C++, C#, or Java).
       # If this step fails, then you should remove it and run the build manually (see below)
       - name: Autobuild
-        uses: github/codeql-action/autobuild@v1
+        uses: github/codeql-action/autobuild@v2
 
       # ℹ️ Command-line programs to run using the OS shell.
       # 📚 https://git.io/JvXDl
@@ -66,4 +66,4 @@ jobs:
       #   make release
 
       - name: Perform CodeQL Analysis
-        uses: github/codeql-action/analyze@v1
+        uses: github/codeql-action/analyze@v2

config/chips/C011xx.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32C011xx device
+#
+dev_type STM32C011xx
+ref_manual_id 0490
+chip_id 0x453                // STM32_CHIPID_C011xx
+flash_type C0
+flash_size_reg 0x1fff75a0
+flash_pagesize 0x800         // 2 KB
+sram_size 0x1800             // 6 KB
+bootrom_base 0x1fff0000
+bootrom_size 0x1800          // 6 KB
+option_base 0x1fff7800       // STM32_C0_OPTION_BYTES_BASE
+option_size 0x80             // 128 B
+flags none

config/chips/C031xx.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32C031xx device
+#
+dev_type STM32C031xx
+ref_manual_id 0490
+chip_id 0x453                // STM32_CHIPID_C031xx
+flash_type C0
+flash_size_reg 0x1fff75a0
+flash_pagesize 0x800         // 2 KB
+sram_size 0x3000             // 12 KB
+bootrom_base 0x1fff0000
+bootrom_size 0x1800          // 6 KB
+option_base 0x1fff7800       // STM32_C0_OPTION_BYTES_BASE
+option_size 0x80             // 128 B
+flags none

config/chips/L45x_L46x.chip

@@ -12,3 +12,5 @@ bootrom_size 0x7000          // 28 KB
 option_base 0x0
 option_size 0x0
 flags swo
+otp_base 0x1fff7000
+otp_size 0x400         // 1 KB

config/chips/L496x_L4A6x.chip

@@ -12,3 +12,5 @@ bootrom_size 0x7000          // 28 KB
 option_base 0x1fff7800       // STM32_L4_OPTION_BYTES_BASE
 option_size 0x4              // 4 B
 flags swo
+otp_base 0x1fff7000
+otp_size 0x400         // 1 KB

config/chips/U535_U545.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32U535 / STM32U545 device
+#
+dev_type STM32U535_U545
+ref_manual_id 0456
+chip_id 0x455                // STM32U535/545
+flash_type L5_U5_H5
+flash_size_reg 0x0bfa07a0
+flash_pagesize 0x2000        // 8 KB
+sram_size 0x44800            // 274 KB
+bootrom_base 0x0bf90000
+bootrom_size 0x8000          // 32 KB
+option_base 0x0
+option_size 0x0
+flags swo dualbank

config/chips/U55Fx_U5Gx.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32U5Fx / STM32U5Gx device
+#
+dev_type STM32U5Fx_U5Gx
+ref_manual_id 0456
+chip_id 0x476                // STM32U5Fx5/5Gx
+flash_type L5_U5_H5
+flash_size_reg 0x0bfa07a0
+flash_pagesize 0x2000        // 8 KB
+sram_size 0x2f4800           // 3026 KB
+bootrom_base 0x0bf90000
+bootrom_size 0x8000          // 32 KB
+option_base 0x0
+option_size 0x0
+flags swo dualbank

config/chips/U5x5.chip → config/chips/U575_U585.chip

@@ -1,8 +1,8 @@
-# Chip-ID file for STM32U5x5 device
+# Chip-ID file for STM32U575 / STM32U585 device
 #
-dev_type STM32U5x5
+dev_type STM32U575_U585
 ref_manual_id 0456
-chip_id 0x482                // STM32_CHIPID_U5x5
+chip_id 0x482                // STM32U575/585
 flash_type L5_U5_H5
 flash_size_reg 0x0bfa07a0
 flash_pagesize 0x2000        // 8 KB
@@ -11,4 +11,4 @@ bootrom_base 0x0bf90000
 bootrom_size 0x10000         // 64 KB
 option_base 0x0
 option_size 0x0
-flags none
+flags swo dualbank

config/chips/U59x_U5Ax.chip

@@ -0,0 +1,14 @@
+# Chip-ID file for STM32U59x / STM32U5Ax device
+#
+dev_type STM32U59x_U5Ax
+ref_manual_id 0456
+chip_id 0x481                // STM32U59x/5Ax
+flash_type L5_U5_H5
+flash_size_reg 0x0bfa07a0
+flash_pagesize 0x2000        // 8 KB
+sram_size 0x274800           // 2514 KB
+bootrom_base 0x0bf90000
+bootrom_size 0x8000          // 32 KB
+option_base 0x0
+option_size 0x0
+flags swo dualbank

doc/supported_devices.md

@@ -6,6 +6,7 @@ More commonly these are:
 | Product-Family | ARM Cortex Core | Product Line                                               |
 | -------------- | --------------- | ---------------------------------------------------------- |
 | STM32F0        | M0              |                                                            |
+| STM32C0        | M0+             |                                                            |
 | STM32G0        | M0+             |                                                            |
 | STM32L0        | M0+             |                                                            |
 | STM32F10**0**  | M3              | Value line                                                 |

inc/stlink.h

@@ -232,6 +232,9 @@ struct _stlink {
     uint32_t chip_flags;         // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx
 
     uint32_t max_trace_freq;     // set by stlink_open_usb()
+
+    uint32_t otp_base;
+    uint32_t otp_size;
 };
 
 /* Functions defined in common.c */

inc/stm32.h

@@ -51,17 +51,18 @@ enum stm32_core_id {
 /* STM32 flash types */
 enum stm32_flash_type {
     STM32_FLASH_TYPE_UNKNOWN   =  0,
-    STM32_FLASH_TYPE_F0_F1_F3  =  1,
-    STM32_FLASH_TYPE_F1_XL     =  2,
-    STM32_FLASH_TYPE_F2_F4     =  3,
-    STM32_FLASH_TYPE_F7        =  4,
-    STM32_FLASH_TYPE_G0        =  5,
-    STM32_FLASH_TYPE_G4        =  6,
-    STM32_FLASH_TYPE_H7        =  7,
-    STM32_FLASH_TYPE_L0_L1     =  8,
-    STM32_FLASH_TYPE_L4        =  9,
-    STM32_FLASH_TYPE_L5_U5_H5  = 10,
-    STM32_FLASH_TYPE_WB_WL     = 11,
+    STM32_FLASH_TYPE_C0        =  1,
+    STM32_FLASH_TYPE_F0_F1_F3  =  2,
+    STM32_FLASH_TYPE_F1_XL     =  3,
+    STM32_FLASH_TYPE_F2_F4     =  4,
+    STM32_FLASH_TYPE_F7        =  5,
+    STM32_FLASH_TYPE_G0        =  6,
+    STM32_FLASH_TYPE_G4        =  7,
+    STM32_FLASH_TYPE_H7        =  8,
+    STM32_FLASH_TYPE_L0_L1     =  9,
+    STM32_FLASH_TYPE_L4        = 10,
+    STM32_FLASH_TYPE_L5_U5_H5  = 11,
+    STM32_FLASH_TYPE_WB_WL     = 12,
 };
 
 /* STM32 chip-ids */
@@ -102,6 +103,7 @@ enum stm32_chipids {
     STM32_CHIPID_F0               = 0x440,
     STM32_CHIPID_F412             = 0x441,
     STM32_CHIPID_F09x             = 0x442,
+    STM32_CHIPID_C011xx           = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */
     STM32_CHIPID_F0xx_SMALL       = 0x444,
     STM32_CHIPID_F04              = 0x445,
     STM32_CHIPID_F303_HD          = 0x446, /* high density */
@@ -111,6 +113,8 @@ enum stm32_chipids {
     STM32_CHIPID_H74xxx           = 0x450, /* RM0433, p.3189 */
     STM32_CHIPID_F76xxx           = 0x451,
     STM32_CHIPID_F72xxx           = 0x452, /* Nucleo F722ZE board */
+    STM32_CHIPID_C031xx           = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */
+    STM32_CHIPID_U535_U545        = 0x455, /* RM0456, p.3604 */
     STM32_CHIPID_G0_CAT4          = 0x456, /* G051/G061 */
     STM32_CHIPID_L0_CAT1          = 0x457,
     STM32_CHIPID_F410             = 0x458,
@@ -126,16 +130,20 @@ enum stm32_chipids {
     STM32_CHIPID_L4Rx             = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
     STM32_CHIPID_L4PX             = 0x471, /* RM0432, p.2247 */
     STM32_CHIPID_L5x2xx           = 0x472, /* RM0438, p.2157 */
+    STM32_CHIPID_U5Fx_U5Gx        = 0x476, /* RM0456, p.3604 */
     STM32_CHIPID_G4_CAT4          = 0x479,
     STM32_CHIPID_H7Ax             = 0x480, /* RM0455, p.2863 */
-    STM32_CHIPID_U5x5             = 0x482, /* RM0456, p.2991 */
+    STM32_CHIPID_U59x_U5Ax        = 0x481, /* RM0456, p.3604 */
+    STM32_CHIPID_U575_U585        = 0x482, /* RM0456, p.3604 */
     STM32_CHIPID_H72x             = 0x483, /* RM0468, p.3199 */
     STM32_CHIPID_H5xx             = 0x484, /* RM0481, p.3085 */
     STM32_CHIPID_WB55             = 0x495,
     STM32_CHIPID_WLE              = 0x497,
 };
 
 /* Constant STM32 option bytes base memory address */
+#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800)
+
 #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14)
 
 #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c)
@@ -189,6 +197,9 @@ enum stm32_chipids {
 #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11
 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12
 
+#define STM32C0_RCC_AHBENR 0x40021038         // RM0490 (revision 3), section 5.4.25 "RCC register map"
+#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map"
+
 #define STM32F1_RCC_AHBENR 0x40021014
 #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 

inc/stm32flash.h

@@ -58,6 +58,30 @@
 #define FLASH_OBR_OFF ((uint32_t)0x1c)
 #define FLASH_WRPR_OFF ((uint32_t)0x20)
 
+// == STM32C0 == (RM0490)
+// C0 Flash registers
+#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000)
+#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08)
+#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C)
+#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10)
+#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14)
+#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20)
+
+// C0 Flash control register
+#define FLASH_C0_CR_PNB 3
+#define FLASH_C0_CR_STRT 16
+#define FLASH_C0_CR_OPTSTRT 17
+#define FLASH_C0_CR_OBL_LAUNCH 27
+#define FLASH_C0_CR_OPTLOCK 30
+#define FLASH_C0_CR_LOCK 31
+
+// C0 Flash status register
+#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3]
+#define FLASH_C0_SR_PROGERR 3
+#define FLASH_C0_SR_WRPERR 4
+#define FLASH_C0_SR_PGAERR 5
+#define FLASH_C0_SR_BSY 16
+
 // == STM32F0 ==
 #define FLASH_F0_OPTKEY1 0x45670123
 #define FLASH_F0_OPTKEY2 0xcdef89ab

src/st-flash/flash.c

@@ -61,6 +61,8 @@ static void usage(void) {
     puts("example write option control register1 byte:  ./st-flash --area=optcr write 0xXXXXXXXX");
     puts("example read option control register1 byte:  ./st-flash --area=optcr1 read");
     puts("example write option control register1 byte:  ./st-flash --area=optcr1 write 0xXXXXXXXX");
+    puts("example read OTP area:  ./st-flash --area=otp read [path]");
+    puts("example write OTP area: ./st-flash --area=otp write [path] 0xXXXXXXXX");
 }
 
 int32_t main(int32_t ac, char** av) {
@@ -180,6 +182,18 @@ int32_t main(int32_t ac, char** av) {
             DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val);
 
             err = stlink_write_option_bytes_boot_add32(sl, o.val);
+        } else if (o.area == FLASH_OTP) {
+            if(sl->otp_base == 0) {
+                err = -1;
+                printf("OTP Write NOT implemented\n");
+                goto on_error;
+            }
+            err = stlink_fwrite_flash(sl, o.filename,  o.addr);
+
+            if (err == -1) {
+                printf("stlink_fwrite_flash() == -1\n");
+                goto on_error;
+            }
         } else {
             err = -1;
             printf("Unknown memory region\n");
@@ -284,6 +298,17 @@ int32_t main(int32_t ac, char** av) {
             } else {
                 printf("%08x\n",option_byte);
             }
+        } else if (o.area == FLASH_OTP) {
+            if(sl->otp_base == 0) {
+                err = -1;
+                printf("OTP Read NOT implemented\n");
+                goto on_error;
+            }
+            err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size);
+            if (err == -1) {
+                printf("could not read OTP area (%d)\n", err);
+                goto on_error;
+            }
         }
     }
 

src/st-flash/flash_opts.c

@@ -288,8 +288,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) {
 
             break;
         } else if (o->area == FLASH_OTP) {
-            return bad_arg("TODO: otp not implemented yet");
-            if (ac > 1) { return invalid_args("otp read: [path]"); }
+            if (ac > 1 || ac ==0 ) { return invalid_args("otp read: [path]"); }
             if (ac > 0) { o->filename = av[0]; }
             break;
         } else if (o->area == FLASH_OPTION_BYTES) {

src/stlink-gui/gui.c

@@ -313,7 +313,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) {
 	  goto out_input;
 	}
 
-        gui->file_mem.size   = (gsize) file_info;
+        gui->file_mem.size   = file_size;
         gui->file_mem.memory = g_malloc(gui->file_mem.size);
 
         for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) {

src/stlink-lib/calculate.c

@@ -66,7 +66,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
   if (sl->chip_id == STM32_CHIPID_L4 ||
       sl->chip_id == STM32_CHIPID_L496x_L4A6x ||
       sl->chip_id == STM32_CHIPID_L4Rx) {
-    // this chip use dual banked flash
+    // these chips use dual bank flash
     if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) {
       uint32_t banksize = sl->flash_size / 2;
 

src/stlink-lib/chipid.c

@@ -34,6 +34,8 @@ void dump_a_chip(struct stlink_chipid_params *dev) {
   DLOG("option_base 0x%x\n", dev->option_base);
   DLOG("option_size 0x%x\n", dev->option_size);
   DLOG("flags %d\n\n", dev->flags);
+  DLOG("otp_base %d\n\n", dev->otp_base);
+  DLOG("otp_size %d\n\n", dev->otp_size);
 }
 
 struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) {
@@ -97,7 +99,9 @@ void process_chipfile(char *fname) {
       buf[strlen(buf) - 1] = 0; // chomp newline
       sscanf(buf, "%*s %n", &nc);
       // Match human readable flash_type with enum stm32_flash_type { }.
-      if (strcmp(value, "F0_F1_F3") == 0) {
+      if(strcmp(value, "C0") == 0) {
+        ts->flash_type = STM32_FLASH_TYPE_C0;
+      } else if (strcmp(value, "F0_F1_F3") == 0) {
         ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3;
       } else if (strcmp(value, "F1_XL") == 0) {
         ts->flash_type = STM32_FLASH_TYPE_F1_XL;
@@ -182,6 +186,18 @@ void process_chipfile(char *fname) {
       }
 
       sscanf(value, "%x", &ts->flags);
+    } else if (strcmp(word, "otp_base") == 0) {
+      buf[strlen(buf) - 1] = 0; // chomp newline
+      sscanf(buf, "%*s %n", &nc);
+      if (sscanf(value, "%i", &ts->otp_base) < 1) {
+        fprintf(stderr, "Failed to parse option size\n");
+      }
+    } else if (strcmp(word, "otp_size") == 0) {
+      buf[strlen(buf) - 1] = 0; // chomp newline
+      sscanf(buf, "%*s %n", &nc);
+      if (sscanf(value, "%i", &ts->otp_size) < 1) {
+        fprintf(stderr, "Failed to parse option size\n");
+      }
     } else {
       fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word);
     }