Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fixed support for STM32U5 chips #1355

Merged
merged 3 commits into from
Nov 23, 2023
Merged

Fixed support for STM32U5 chips #1355

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
e286f24
Fixing support for U5 chips (original U5x5.chip was not handling all …
marcelobarrosufu Nov 14, 2023
5df53ad
Missing swo and dualback flags in U6 chip models
marcelobarrosufu Nov 14, 2023
ed558c9
Merge branch 'develop' into develop
Nightwalker-87 Nov 23, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 14 additions & 0 deletions config/chips/U535_U545.chip
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
# Chip-ID file for STM32U535 / STM32U545 device
#
dev_type STM32U535_U545
ref_manual_id 0456
chip_id 0x455 // STM32U535/545
flash_type L5_U5_H5
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
sram_size 0x44800 // 274 KB
bootrom_base 0x0bf90000
bootrom_size 0x8000 // 32 KB
option_base 0x0
option_size 0x0
flags swo dualbank
14 changes: 14 additions & 0 deletions config/chips/U55Fx_U5Gx.chip
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
# Chip-ID file for STM32U5Fx / STM32U5Gx device
#
dev_type STM32U5Fx_U5Gx
ref_manual_id 0456
chip_id 0x476 // STM32U5Fx5/5Gx
flash_type L5_U5_H5
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
sram_size 0x2f4800 // 3026 KB
bootrom_base 0x0bf90000
bootrom_size 0x8000 // 32 KB
option_base 0x0
option_size 0x0
flags swo dualbank
8 changes: 4 additions & 4 deletions config/chips/U5x5.chip → config/chips/U575_U585.chip
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
# Chip-ID file for STM32U5x5 device
# Chip-ID file for STM32U575 / STM32U585 device
#
dev_type STM32U5x5
dev_type STM32U575_U585
ref_manual_id 0456
chip_id 0x482 // STM32_CHIPID_U5x5
chip_id 0x482 // STM32U575/585
flash_type L5_U5_H5
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
Expand All @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000
bootrom_size 0x10000 // 64 KB
option_base 0x0
option_size 0x0
flags none
flags swo dualbank
14 changes: 14 additions & 0 deletions config/chips/U59x_U5Ax.chip
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
# Chip-ID file for STM32U59x / STM32U5Ax device
#
dev_type STM32U59x_U5Ax
ref_manual_id 0456
chip_id 0x481 // STM32U59x/5Ax
flash_type L5_U5_H5
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
sram_size 0x274800 // 2514 KB
bootrom_base 0x0bf90000
bootrom_size 0x8000 // 32 KB
option_base 0x0
option_size 0x0
flags swo dualbank
5 changes: 4 additions & 1 deletion inc/stm32.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,7 @@ enum stm32_chipids {
STM32_CHIPID_F76xxx = 0x451,
STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */
STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */
STM32_CHIPID_U535_U545 = 0x455, /* RM0456, p.3604 */
STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */
STM32_CHIPID_L0_CAT1 = 0x457,
STM32_CHIPID_F410 = 0x458,
Expand All @@ -129,9 +130,11 @@ enum stm32_chipids {
STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */
STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */
STM32_CHIPID_U5Fx_U5Gx = 0x476, /* RM0456, p.3604 */
STM32_CHIPID_G4_CAT4 = 0x479,
STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */
STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */
STM32_CHIPID_U59x_U5Ax = 0x481, /* RM0456, p.3604 */
STM32_CHIPID_U575_U585 = 0x482, /* RM0456, p.3604 */
STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */
STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */
STM32_CHIPID_WB55 = 0x495,
Expand Down
12 changes: 8 additions & 4 deletions src/stlink-lib/common_flash.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1132,10 +1132,12 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
val &= ~(0x7F << 3);
val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER);
stlink_write_debug32(sl, FLASH_Gx_CR, val);
// STM32L5x2xx has two banks with 2k pages or single with 4k pages
// STM32H5xx, STM32U535, STM32U545, STM32U575 or STM32U585 have 2 banks with 8k pages
} else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) {
uint32_t flash_page;
stlink_read_debug32(sl, FLASH_L5_NSCR, &val);
if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) {
if ((sl->flash_pgsz == 0x800 || sl->flash_pgsz == 0x2000) && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) {
flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / sl->flash_pgsz;
// set bank 2 for erasure
val |= (1 << FLASH_L5_NSCR_NSBKER);
Expand All @@ -1144,9 +1146,11 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
// set bank 1 for erasure
val &= ~(1 << FLASH_L5_NSCR_NSBKER);
}
// sec 6.9.9
val &= ~(0x7F << 3);
val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER);
// sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but
// the bit position for 8th bit reserved.
// Maybe the best solution is to handle each one separately.
val &= ~(0xFF << 3);
val |= ((flash_page & 0xFF) << 3) | (1 << FLASH_CR_PER);
stlink_write_debug32(sl, FLASH_L5_NSCR, val);
} else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) {
uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz);
Expand Down
Loading