[src] enable XBUS (for testing)

stnolting · Jan 15, 2025 · 6ec2a6b · 6ec2a6b
1 parent 092e6c3
commit 6ec2a6b
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/src/neorv32_verilog_wrapper.vhd b/src/neorv32_verilog_wrapper.vhd
@@ -86,6 +86,11 @@ begin
     DCACHE_EN           => true,        -- implement data cache
     DCACHE_NUM_BLOCKS   => 4,           -- d-cache: number of blocks (min 1), has to be a power of 2
     DCACHE_BLOCK_SIZE   => 64,          -- d-cache: block size in bytes (min 4), has to be a power of 2
+    -- External bus interface (XBUS) --
+    XBUS_EN             => true,        -- implement external memory bus interface?
+    XBUS_TIMEOUT        => 256,         -- cycles after a pending bus access auto-terminates (0 = disabled)
+    XBUS_REGSTAGE_EN    => true,        -- add XBUS register stage
+    XBUS_CACHE_EN       => false,       -- enable external bus cache (x-cache)
     -- Processor peripherals --
     IO_CLINT_EN         => true,        -- implement core local interruptor (CLINT)?
     IO_UART0_EN         => true,        -- implement primary universal asynchronous receiver/transmitter (UART0)?