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Implement SPIRegister trait
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sunsided committed Jul 5, 2024

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sunsided Markus Mayer
1 parent 56e9cbf commit 2d7f92a
Showing 8 changed files with 903 additions and 1,703 deletions.
3 changes: 2 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -18,7 +18,8 @@ defmt = ["dep:defmt"]
[dependencies]
bitfield-struct = "0.8.0"
defmt = { version = "0.3.8", optional = true }
hardware-registers = "0.1.0"
# hardware-registers = "0.1.0"
hardware-registers = { git = "http://github.com/sunsided/hardware-registers", features = ["i2c", "spi"] }

[package.metadata.docs.rs]
all-features = true
1,028 changes: 0 additions & 1,028 deletions src/accel.rs

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152 changes: 0 additions & 152 deletions src/accel/types.rs

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709 changes: 709 additions & 0 deletions src/gyro.rs

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15 changes: 13 additions & 2 deletions src/lib.rs
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@@ -13,7 +13,9 @@
pub mod prelude {
pub use crate::{Register, WritableRegister};
pub use hardware_registers::i2c::*;
pub use hardware_registers::register_address::{RegisterAddress6, RegisterAddress8};
pub use hardware_registers::sizes::R1;
pub use hardware_registers::spi::*;
pub use hardware_registers::{FromBits, HardwareRegister, ToBits, WritableHardwareRegister};
}

@@ -37,6 +39,15 @@ macro_rules! readable_register {
$crate::prelude::RegisterAddress8::new(($addr).addr());
}

impl $crate::prelude::SPIRegister<$crate::prelude::RegisterAddress6, $crate::prelude::R1>
for $type
{
type Backing = u8;

const REGISTER_ADDRESS: $crate::prelude::RegisterAddress6 =
$crate::prelude::RegisterAddress6::new(($addr).addr());
}

impl $crate::prelude::ToBits for $type {
type Target = u8;

@@ -67,8 +78,8 @@ macro_rules! writable_register {
};
}

pub mod accel;
pub mod mag;
pub mod gyro;
mod types;

/// A sensor register.
pub trait Register: prelude::I2CRegister8<prelude::DeviceAddress7> + From<u8> + Into<u8> {}
413 changes: 0 additions & 413 deletions src/mag.rs

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107 changes: 0 additions & 107 deletions src/mag/types.rs

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179 changes: 179 additions & 0 deletions src/types.rs
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@@ -0,0 +1,179 @@
//! Types used in the Gyroscope registers.
/// Gyroscope Output Data Rate
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum OutputDataRate {
/// 95 Hz (`0b00`)
Hz95 = 0b00,
/// 190 Hz(`0b01`)
Hz190 = 0b01,
/// 380 Hz(`0b10`)
Hz380 = 0b10,
/// 760 Hz(`0b11`)
Hz760 = 0b11,
}

impl OutputDataRate {
/// Converts the value into an `u8`.
pub const fn into_bits(self) -> u8 {
self as u8
}

pub(crate) const fn from_bits(value: u8) -> Self {
match value {
0b00 => OutputDataRate::Hz95,
0b01 => OutputDataRate::Hz190,
0b10 => OutputDataRate::Hz380,
0b11 => OutputDataRate::Hz760,
_ => unreachable!(),
}
}
}

/// Bandwidth
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Bandwidth {
/// * 12.5 at 95 Hz ([`OutputDataRate::Hz95`])
/// * 12.5 at 190 Hz ([`OutputDataRate::Hz190`])
/// * 20 at 380 Hz ([`OutputDataRate::Hz380`])
/// * 30 at 760 Hz ([`OutputDataRate::Hz760`])
Bw00 = 0b00,
/// * 25 at 95 Hz ([`OutputDataRate::Hz95`])
/// * 25 at 190 Hz ([`OutputDataRate::Hz190`])
/// * 25 at 380 Hz ([`OutputDataRate::Hz380`])
/// * 35 at 760 Hz ([`OutputDataRate::Hz760`])
Bw01 = 0b01,
/// * 25 at 95 Hz ([`OutputDataRate::Hz95`])
/// * 25 at 190 Hz ([`OutputDataRate::Hz190`])
/// * 25 at 380 Hz ([`OutputDataRate::Hz380`])
/// * 35 at 760 Hz ([`OutputDataRate::Hz760`])
Bw10 = 0b10,
/// * 25 at 95 Hz ([`OutputDataRate::Hz95`])
/// * 70 at 190 Hz ([`OutputDataRate::Hz190`])
/// * 100 at 380 Hz ([`OutputDataRate::Hz380`])
/// * 100 at 760 Hz ([`OutputDataRate::Hz760`])
Bw11 = 0b11,
}

impl Bandwidth {
/// Converts the value into an `u8`.
pub const fn into_bits(self) -> u8 {
self as u8
}

pub(crate) const fn from_bits(value: u8) -> Self {
match value {
0b00 => Bandwidth::Bw00,
0b01 => Bandwidth::Bw01,
0b10 => Bandwidth::Bw10,
0b11 => Bandwidth::Bw11,
_ => unreachable!(),
}
}
}

/// High-pass filter mode.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum HighpassFilterMode {
/// Normal mode (reset reading `HP_RESET_FILTER`)
NormalModeResetFilter = 0b00,
/// Reference signal for filtering
ReferenceSignal = 0b01,
// Normal mode
NormalMode = 0b10,
/// Autoreset on interrupt event
AutoresetOnInterrupt = 0b11,
}

impl HighpassFilterMode {
/// Converts the value into an `u8`.
pub const fn into_bits(self) -> u8 {
self as u8
}

pub(crate) const fn from_bits(value: u8) -> Self {
match value {
0b00 => HighpassFilterMode::NormalModeResetFilter,
0b01 => HighpassFilterMode::ReferenceSignal,
0b10 => HighpassFilterMode::NormalMode,
0b11 => HighpassFilterMode::AutoresetOnInterrupt,
_ => unreachable!(),
}
}
}

/// Gyroscope sensitivity (full scale selection).
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Sensitivity {
/// 250 dps
G250 = 0b00,
/// 500 dps
G500 = 0b01,
/// 2000 dps
G2000 = 0b10,
/// 2000 dps
G2000_11 = 0b11,
}

impl Sensitivity {
/// Converts the value into an `u8`.
pub const fn into_bits(self) -> u8 {
self as u8
}

pub(crate) const fn from_bits(value: u8) -> Self {
match value {
0b00 => Sensitivity::G250,
0b01 => Sensitivity::G500,
0b10 => Sensitivity::G2000,
0b11 => Sensitivity::G2000_11,
_ => unreachable!(),
}
}
}

/// FIFO mode configuration.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum FifoMode {
/// Bypass mode (`0b000`)
///
/// Bypass the FIFO and store data directly in the output registers.
Bypass = 0b000,
/// FIFO mode (`0b001`)
#[allow(clippy::upper_case_acronyms)]
FIFO = 0b001,
/// Stream mode (`0b010`)
Stream = 0b010,
/// Stream-to-FIFO mode (`0b011`)
StreamToFifo = 0b011,
/// Bypass-to-Stream mode (`0b100`)
BypassToStream = 0b100,
}

impl FifoMode {
/// Converts the value into an `u8`.
pub const fn into_bits(self) -> u8 {
self as u8
}

pub(crate) const fn from_bits(value: u8) -> Self {
match value {
0b000 => FifoMode::Bypass,
0b001 => FifoMode::FIFO,
0b010 => FifoMode::Stream,
0b011 => FifoMode::StreamToFifo,
0b100 => FifoMode::BypassToStream,
_ => unreachable!(),
}
}
}

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