This is just a toy project to see what control signals should be used to sync parallel stages and to understand ways to create a RISC-V system.

Not all RV32I instructions are implemented, only the ones needed to run the tests

To build:

• mkdir build
• cd build
• cmake ../ --preset=[release|debug]
• make -j

To run:

• ./Riscv_Emu

To build the tests:

• cd tests
• make all - to build all tests
• cd ts_[test-name]
• make all - to build only the current test

RISCV MANUAL