Add bitmanip extension support #525
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Introduce the rv_ctz() function to compute the count of trailing zeros in a 32-bit integer. This function serves as a prerequisite for implementing the ctz instruction in the RISC-V Zbb extension.
Introduce the rv_popcount() function to compute the population count (number of set bits) in a 32-bit integer. This function is a prerequisite for implementing the cpop instruction in the RISC-V Zbb extension.
Add support for the RISC-V Zba address generation extension. These instructions combine shift and addition operations, enabling efficient address calculation in pointer arithmetic and memory access patterns. Supporting the Zba extension improves compatibility with the RISC-V specification and enables optimized handling of address generation tasks.
jserv
reviewed
Dec 22, 2024
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Benchmarks
| Benchmark suite | Current: 73dea0c | Previous: e7ded18 | Ratio |
|---|---|---|---|
Dhrystone |
1337 Average DMIPS over 10 runs |
1301 Average DMIPS over 10 runs |
0.97 |
Coremark |
975.043 Average iterations/sec over 10 runs |
977.65 Average iterations/sec over 10 runs |
1.00 |
This comment was automatically generated by workflow using github-action-benchmark.
jserv
requested changes
Dec 23, 2024
ChinYikMing
reviewed
Dec 23, 2024
Add support for the RISC-V Zbb basic bit-manipulation extension. This extension introduces fundamental bitwise operations such as bit counting, bit field extraction, and bit rotation, enabling efficient data manipulation and low-level computation. Supporting the Zbb extension improves compatibility with the RISC-V specification and enables optimized handling of bitwise operations in a wide range of applications.
Add support for the RISC-V Zbc carry-less multiplication extension. This extension introduces instructions for carry-less multiplication, enabling efficient operations in cryptographic algorithms, error-correcting codes, and other specialized applications. Supporting the Zbc extension improves compatibility with the RISC-V specification and enables optimized handling of carry-less multiplication tasks.
Add support for the RISC-V Zbs single-bit instructions extension. This extension introduces instructions for efficient manipulation of individual bits, enabling optimized operations in bit-level processing and control. Supporting the Zbs extension improves compatibility with the RISC-V specification and enhances performance in tasks requiring precise single-bit operations.
Update the RISC-V architectural test to include support for testing the Zba, Zbb, Zbc, and Zbs extensions. With this change, users can run tests for these extensions using the following command: make arch-test RISCV_DEVICE=IMZbaZbbZbcZbs
Add tests for the Zba, Zbb, Zbc, and Zbs extensions to the CI pipeline, ensuring that these extensions are validated automatically during continuous integration.
Update the README to include details about the RISC-V Zba, Zbb, Zbc, and Zbs bit manipulation extensions.
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Add support for the RISC-V bitmanip extensions Zba, Zbb, Zbc, and Zbs. These extensions optimize bitwise operations such as memory addressing, bitfield manipulation, counting leading/trailing zeros, and extracting subfields. All implementations have been validated through architectural tests, ensuring their correctness and reliability in emulating these operations.