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Implemented riscv64 syscall support by modifying source code of opensbi and sbi-spec #69

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merged 1 commit into from
May 9, 2024

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Sssssaltyfish
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More precisely speaking, by having opensbi to pass unknown ecall to ruxos trap handler.
Note that due to the change of [patch.crates.io] in /Cargo.toml, CIs won't pass unless we init submodules before tests in CI procedures. Also, I couldn't find a cfg(target_arch = "riscv64") version of [patch.crates.io].

Besides this modification, this PR does the following jobs:

  1. opensbi and sbi-spec (used by sbi-rt used by ruxhal) are integrated via git submodule.

  2. added 1000 to eid in sbi calls to distinguish sbi calls from posix sysacalls.

  3. changed the default size of physical memory to 1G, as more would cause dtb page error in my environment.

api/ruxos_posix_api/src/imp/pthread/mod.rs Outdated Show resolved Hide resolved
api/ruxos_posix_api/src/imp/pthread/mod.rs Outdated Show resolved Hide resolved
platforms/riscv64-qemu-virt.toml Outdated Show resolved Hide resolved
@Sssssaltyfish
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As all tests are passed and I've successfully done a clean build under riscv64 in my environment, I guess this PR is ready to be merged. Please tell me if there's any improvement I can do before rebasing it into one commit.

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@coolyjg coolyjg left a comment

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Just a minor suggestion.
I think it is okay to merge. Please rebase into one commit.

modules/ruxhal/src/arch/riscv/trap.rs Outdated Show resolved Hide resolved
Besides, this commit also contains the following changes:

1. Added build suffix to musl to distinguish archs and modes.

2. Implemented prebuild hook so that opensbi would be cloned
    while building under riscv64.

3. Fixed boot page table in riscv64 so that dtb won't cause
    a page fault.

4. Updated github CI under riscv64.
@coolyjg coolyjg merged commit 8a729f8 into syswonder:dev May 9, 2024
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@coolyjg coolyjg mentioned this pull request Jun 1, 2024
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2 participants