Hey! I am Chaitra

Hope you coverage all my repos. Welcome!

🚀 About Me

I'm a Design Verification Engineer, and have a keen interest in anything and everthing VLSI!

I am currently working on projects that make me familiar with UVM.

🛠 Skills

• Verilog
• System Verilog
• UVM
• Xilinx Ise
• QuestaSim
• Synopsys VCS
• Cadence Virtuoso

🔗 Links

Thank you for visiting