A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded
fpga
hls
xilinx
vivado
xilinx-fpga
basys3
xilinx-vivado
axi
artix
axi-stream
vivado-ip-integrator
artix-7
xilinx-hls
vitis
axi-lite
xilinx-vitis
vivado-vitis
vitis-hls
axi-memory-mapped
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Updated
Nov 21, 2023 - TeX