Verilog implementation of an N-bit arithmetic/logical shifter and rotator supporting left/right shifts and rotations. Useful for CPU datapaths and digital design applications.

Verilog implementation of an N-bit ALU supporting operations like AND, OR, ADD, SUB, SLT, and functions with complemented inputs. Ideal for CPU design and digital system projects.

This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7

Implements a 3-to-8 line decoder using gate-level logic in Verilog. Converts a 3-bit binary input into a corresponding one-hot output across 8 lines (D0–D7). Features: Gate-level realization, Truth table-based logic equations, Behavioral simulation with 8 input combinations

Verilog-based priority encoder that takes 8 input lines (D0–D7) and produces a 3-bit binary output indicating the highest priority active input. Features: Priority logic ensures higher-priority signals override others. Logical equations used for encoding. Testbench covers various priority scenarios

Verilog implementation of a 4-bit adder/subtractor using combinational logic with testbench and simulation output.

Verilog implementation of an N-bit comparator with outputs for equal, not equal, greater than, less than, greater than or equal, and less than or equal.

Source for the Experience Notation documentation site. Includes language spec, tutorials, and examples.

Implements a hierarchical 1-to-16 demultiplexer using a 1x2 and two 1x8 demux blocks in Verilog. Directs a single input signal to one of 16 outputs based on select lines. Features: Hierarchical Verilog modules (1x2 and 1x8), Behavioral testbench for all 16 select combinations, Graph-based output verification

Experience Notation (.expn) is a human-readable DSL for modelling structured user journeys. It bridges qualitative design with simulation and LLM-driven analysis.

SystemVerilog implementation of an unsigned binary divider for 4-bit inputs using a hardware-friendly algorithm.