A flexible framework for analyzing and transforming FPGA netlists. Official repository.
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Updated
Feb 12, 2025 - Python
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
A hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.
intro to electronics & robotics
A validated design database and simulation workflow software for superconducting quantum hardware
Ladder Diagram editor implementation using Qt. See: https://code.qt.io/cgit/qt/qtbase.git/tree/examples/widgets/graphicsview/diagramscene?h=5.14
An asset which include circuit symbols for drawing schematics and block diagrams with Affinity Designer
Circuitron: Agentic PCB Design Accelerator — Generate, plan, and layout circuits from natural language prompts.
微电子和集成电路自学指南
A basic USB mouse PCB based on the PAW3526D8-FJY2 Sensor.
A plugin for Obsidian to draw circuits on a canvas.
All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.
Connection Machine is an open-source desktop application for designing and simulating digital circuits at scale.
An LTspice project which contains third-order Butterworth filters built both using an inductor and a current conveyor.
This library is an attempt to make transistor sizing for Analog design less painful.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.
Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
A breadboard-based circuit designer and simulator written in Java
Quantum Circuit Designer: A gymnasium-based set of environments for benchmarking reinforcement learning for quantum circuit design.
A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog
Introductory course to Self Timed Circuits
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