designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE
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Apr 23, 2020 - Verilog
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controlpath
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Digital circuit description to perform multiplication with data_path and control_path using verilog
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Jul 30, 2020 - Verilog
4 staged MIPS verilog processor
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Jun 24, 2019 - Verilog
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm
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May 28, 2024 - Verilog
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